Sequential logic circuit having state hold circuits

Details Sequential logic circuit having state hold circuits Sequential logic circuit having state hold circuits

1991-11-26

1995-06-20

Westin, Edward P.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

377122, 377127, 377128, 326 93, G11C 1900, G11C 1928

Patent

active

054266823

ABSTRACT:
A sequential logic circuit includes N state hold circuit where N is an integer. Each of the state hold circuits has a first input terminal, a second input terminal and an output terminal. The state hold circuits are cascaded via the respective first input terminals. The second input terminals of the state hold circuits receive a first clock signal. The first input terminal of one of the state hold circuits in a first stage receives a data signal. The output signal is obtained via the output terminal of one of the state hold circuits in a final stage. Each of the state hold circuits has the following truth table:

REFERENCES:
patent: 3631260 (1971-12-01), Yoshino
patent: 4250406 (1981-02-01), Alaspa
patent: 5015874 (1991-05-01), Takatsu

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