Sequential logic circuit having state hold circuits

Details Sequential logic circuit having state hold circuits Sequential logic circuit having state hold circuits

1991-11-26

1993-06-22

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 3072722, H03K 19173

Patent

active

052218660

ABSTRACT:
A sequential logic circuit includes first, second and third state hold circuits, each having a first input terminal, a second input terminal and an output terminal. The first input terminal of the first state hold circuit receives a clock signal, and the second input terminal of the first state hold circuit and the first input terminal of the second state hold circuit receive a data signal. The second input terminal of the second state hold circuit receives an inverted clock signal corresponding to an inverted version of the clock signal. The output terminal of the first state hold circuit and the output terminal of the second state hold circuit are connected to the first and second input terminals of the third state hold circuit, respectively. An output signal of the sequential logic circuit is output via the output terminal of the third state hold circuit. Each of the first, second and third state hold circuits has the following truth table:

REFERENCES:
patent: 3631260 (1971-12-01), Yoshino
patent: 4348597 (1982-09-01), Weber
patent: 5015874 (1991-05-01), Takatsu

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