Sequential decoder for decoding of convolutional codes

Details Sequential decoder for decoding of convolutional codes Sequential decoder for decoding of convolutional codes

2001-10-22

2004-02-10

Le, Amanda T. (Department: 2631)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C714S791000, C714S796000

Reexamination Certificate

active

06690752

ABSTRACT:

TECHNICAL FIELD
This invention relates to digital communications, and more particularly to sequential decoders for convolutional codes.
BACKGROUND
Energy consumption in portable, battery-powered communication devices is increasingly important. Traditional design techniques have led to decoders that use fixed-complexity algorithms such as the Viterbi algorithm that perform a fixed amount of effort, and thereby consume a relatively constant amount of power, regardless of the prevailing signal-to-noise ratio (SNR) and/or fidelity requirements. The Viterbi algorithm is an optimal tree-search algorithm that determines the complete path, from the root to leaf, with maximum path metric. The properties of such fixed complexity algorithms that are traditionally viewed as advantages are regular structure, optimal decoding, and deterministic processing delay. However, since the amount of decoding effort of a fixed complexity algorithm is independent of signal-to-noise ratio (SNR) and fidelity requirements, decoders based on fixed complexity algorithms may consume inordinate amounts of power under some operating conditions such as when the SNR is high.
One example of such an application is mobile communication. In a mobile communication system, the operating characteristics may vary dramatically as a mobile unit moves across a cell. The use of a traditional fixed complexity algorithm, such as the Viterbi algorithm, in a mobile communication system may result in the waste of a significant amount of energy for decoding when the operating conditions are good.
In applications such as mobile communication, conventional sequential decoding techniques have been considered a poor alternative to traditional fixed complexity algorithms. Sequential decoding algorithms are good, suboptimal, tree-search algorithms that find a path with a metric close to the maximum path metric. Although, sequential decoding techniques typically require less average complexity and consume less average power when used with sufficiently high SNR, they are generally limited to non-real-time applications due to degradation of coding gain (at sufficiently high SNR), large variations in the required decoding effort, and associated decoding delay. In fact, when operating below the computational cut-off SNR, the decoding effort associated with conventional sequential decoders may grow prohibitively, leading to overflowing of buffers and an excessive decoded error rate. The large variations in the required decoding effort of conventional sequential decoders have made them considered to be unsuitable for applications that include periodic, hard deadlines such as real-time applications.
SUMMARY
A sequential decoder that may be used for decoding convolutional code is disclosed. The sequential decoder includes a computing device comprising a Fano technique. The Fano technique includes a plurality of variables that are normalized to change a point of reference of the technique. One of the variables is a current node metric. The variables are normalized such that the current node metric is set to approximately zero. Methods for using this decoder in applications that include periodic, hard deadlines such as real-time applications are also presented.


REFERENCES:
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S.K. Singh, P. Thiennviboon, R. Ozdag, S. Tugsinavisut, P.A. Beerel and C.M. Chugg, “Algorithm and Circuit Co-Design for a Low-Power Sequential Decoder”, ASILOMAR'99, pp. 389-394, Oct. 1999.

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