Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal gain processing
Patent
1987-06-01
1989-06-20
Canney, Vincent P.
Dynamic information storage or retrieval
Binary pulse train information signal
Binary signal gain processing
G11B 502
Patent
active
048415138
ABSTRACT:
A sequential buffer device for connection to a serially readable memory. The device has an input for serially receiving successive data frames, which frames contain user data, error detection data and error correction data in a predetermined pattern; a random access memory which is connected to the input in order to store the data of at least one frame received in a byte-wise first write operation, under the control of a byte-wise incrementable address counter; a cyclically operational error detection device which is connected to the input in order to execute an error detection on the basis of the error detection data in a frame received; an error correction device which is bidirectionally connected to the random access memory in order to localize and correct an error under the control of the error correction device and on the basis of the error correction data in the frame; and a first-in-first-out (FIFO) memory having a capacity which equals at the most the capacity of the random access memory. A data input which is connected to a data output of the random access memory in order to execute, in synchronism with the first read operation, a first write operation for writing data from the random access memory into the FIFO memory. The FIFO memory also has a data output for performing a second user read operation asynchronously with respect to the first read-out operation, in order to read data from the FIFO memory.
REFERENCES:
patent: 4672597 (1987-06-01), Yamazaki et al.
patent: 4736352 (1988-04-01), Satoh et al.
Farhangi Hassan
Konings Johan W. M. E.
Canney Vincent P.
Tamoshunas Algy
U.S. Philips Corporation
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