Sequential access LSI memory circuit for pattern generator

Details Sequential access LSI memory circuit for pattern generator Sequential access LSI memory circuit for pattern generator

1985-03-12

1987-07-07

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365189, 365230, 365236, G11C 700, G11C 800, G11C 1140

Patent

active

046791736

ABSTRACT:
In an LSI memory of the invention, in order to decrease the number of input address lines, an address counter having a bit length corresponding to some input address lines is incorporated in the LSI memory to compensate for the number of omitted input address lines. The address counter is counted up in response to a clock pulse supplied through an additional clock input signal line and is initialized in response to a chip enable signal.

REFERENCES:
patent: 3771145 (1973-11-01), Weiner
patent: 3930239 (1975-12-01), Salters et al.
patent: 4412313 (1983-10-01), Ackland et al.
IC Technical Data Toshiba MOS Memory Sixth Edition Mask ROM, pp. 252-255 DRAM, Sep. 1983.

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