Static information storage and retrieval – Addressing – Sequential
Patent
1995-09-12
1997-06-17
Popek, Joseph A.
Static information storage and retrieval
Addressing
Sequential
365221, 365236, G11C 800
Patent
active
056403666
ABSTRACT:
The sequential-access asynchronous memory device comprises an asynchronous double-port random access memory (MVDP), a write address generator (CE) for delivering to the input port of the memory, in response to write enable signals (ATE), successive write address information (ADE) respectively associated with successive data (DE) to be stored sequentially in a predetermined order of writing, a read address generator (CL) for delivering to the output port of the memory, in response to read enable signals (ATL), successive read address information (ADL) respectively associated with successive data (DL) to be read sequentially in a predetermined order of reading, a device for detecting the stability of the address information delivered by the address generators, and a device (GAE, GAL, ST1, ST2) for determining the level of fill of the memory from the stable address information delivered by the address generators.
REFERENCES:
patent: 5274600 (1993-12-01), Ward et al.
patent: 5311475 (1994-05-01), Huang
patent: 5426612 (1995-06-01), Ichige et al.
Majos Jacques
Weil Daniel
France Telecom
Popek Joseph A.
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