Sequence generation for mismatch-shaping circuits

Details Sequence generation for mismatch-shaping circuits Sequence generation for mismatch-shaping circuits

2007-05-09

2008-11-04

Nguyen, Linh V (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S143000, C341S118000, C341S147000, C341S148000

Reexamination Certificate

active

07446688

ABSTRACT:
An embodiment of the present invention is a technique to design a DAC. A double-summed-to-zero (DSTZ) graph is created having a plurality of nodes linked by a plurality of directed branches. The DSTZ graph represents a finite state machine (FSM) that generates a sequence for a switching block used in a mismatch-shaping digital-to-analog converter (DAC). Each of the plurality of nodes represents a state in the FSM. The DSTZ graph has a total work function and a total potential energy summing to zero for a cycle traversal. A switching sequence is generated starting from a reference node in the plurality of nodes in response to an input sequence. The reference node has a zero potential energy.

REFERENCES:
patent: 5404142 (1995-04-01), Adams et al.
patent: 5684482 (1997-11-01), Galton
patent: 6304608 (2001-10-01), Chen et al.
patent: 6628218 (2003-09-01), Brooks et al.
patent: 6697004 (2004-02-01), Galton et al.
patent: 6771199 (2004-08-01), Brooks et al.
patent: 6816097 (2004-11-01), Brooks et al.
patent: 6867721 (2005-03-01), Lin
patent: 7193548 (2007-03-01), Kaplan
patent: 7304593 (2007-12-01), Luecking et al.
patent: 7308032 (2007-12-01), Capofreddi
patent: 2003/0085827 (2003-05-01), Koifman et al.
patent: 2005/0134492 (2005-06-01), Wang et al.
Galton, Ian, “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters”, IEEE Trans. on Circuits and Systems—II, vol. 44, No. 10, pp. 808-817 Oct. 1997.
Welz, Jared, et al., “Necessary and Sufficient Conditions for Mismatch Shaping in a General Class of Multibit DACs”, IEEE Trans. on Circuits and Systems—II, vol. 49, No. 12, pp. 748-759, Dec. 2002.
Welz, Jared, et al., “Simplified Logic for First-Order and Second-Order Mismatch-Shaping digital-to-Analog Converters”, IEEE Trans. on Circuits and Systems—II, vol. 48, No. 11, pp. 1014-1027, Nov. 2001.
Yasuda, Akira, et al., “A Third-Order Delta-Sigma Modulator Using Second-Order Noise Shaping Dynamic Element Matching”, IEEE J. of Solid State Circuits, vol. 33, No. 12, pp. 1879-1886, Dec. 1998.

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