Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1998-05-22
2003-04-29
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C714S794000
Reexamination Certificate
active
06556632
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sequence estimation method and a sequence estimator for estimating a transmitted signal sequence at a receiving side, and more particularly to, a Viterbi equalization method or a Viterbi decoding method, based on a received signal and characteristic of a channel, or a coding rule in a digital data transmission system such as a car cellular telephone.
2. Description of the Prior Art
Usually, in a digital data transmission, a transmitted signal from a transmission side can not be properly received at a receiving side due to a state of the channel or noise, but the transmitted signal is received in a converted form due to the state of the channel or the noise. A model for the converted signal on the channel is depicted in FIG.
16
. As depicted in
FIG. 16
, the input signal is delayed on the channel and combined with a noise. Accordingly, if the transmitted signal is I
k
, a received signal r
k
is expressed by the following formula (1).
r
k
=
∑
i
=
0
L
c
i
I
k
-
i
+
W
k
(
1
)
Where, “L” represents a memory length of the channel making the transmitted signal delay, “c
i
” represents a tap coefficient and “w
k
” represents a noise component. The tap coefficient and the noise component are determined by a characteristic of the channel. If the tap coefficient is read as a decoding rule, the tap coefficient works as a Viterbi decoding. A receiver receives a received signal r
k
and the received signal is estimated by this received signal r
k
and the tap coefficient c
i
. A receiver (a sequence estimator) calculates an estimated value (hereinafter, referred to as “replica”) of a received signal by convoluting a candidate of a transmitted signal and a known tap coefficient as in formula (2).
r
k
e
=
∑
i
=
0
L
c
i
I
k
-
i
e
(
2
)
Furthermore, the sequence estimator calculates an error power between an actual received signal and the replica of the received signal calculated from formula (2).
∑
k
&LeftBracketingBar;
e
k
&RightBracketingBar;
2
=
∑
k
&LeftBracketingBar;
r
k
-
r
k
e
&RightBracketingBar;
2
(
3
)
The sequence estimator searches a candidate of the transmitted signal having a smallest error power calculated from formula (3), and estimates it as a transmitted signal. Processing of the sequence estimation is explained when the memory length L of the channel is expressed as L=2.
FIG. 17
shows a suitable model of the sequence estimator when the memory length L of the channel is 2. The sequence estimator is configured as to reproduce a model similar to that of the channel. An additional device for applying the noise is not necessary for this sequence estimator among the channel models of the channel.
The sequence estimator includes a memory having a memory length the same as that of the channel which receives an estimated value of the transmitted signal, a multiplication device for multiplying the estimated value of the transmitted signal output from the memory by a predetermined tap coefficient, a summing device for calculating a replica of a received signal by summing the multiplied values obtained by the multiplication device, a difference calculation device for calculating the difference between the replica of the received signal output from the summing device and an actual reception signal, and a square summing device for summing the square values output from the difference calculation device. The predetermined tap coefficient set to the multiplication device is the same as the tap coefficient obtained from a characteristic of the channel.
A method for a maximum-likelihood detection according to such a sequence estimator is explained. First, a candidate of the transmitted signal having the transmission sequence length N is received. This candidate of the transmitted signal is input to the memory of the sequence estimator. The multiplication device multiplies each signal output from the memory by tap coefficients C
1
and C
2
. It also multiplies a tap coefficient C
0
by the input signal which does not pass through the memory. The summing device obtains a replica of the received signal by summing all values multiplied by the multiplication device. The difference calculation device obtains the difference between the actual received signal and the replica of the received signal obtained from the summing device.
The square summing device sums the square of the difference value output from the difference calculation device. The square summing device provides a sum of the difference value by summing the sum of the square of the difference between the received signal and the replica of the received signal for all signal sequences. The number of candidates of this transmitted signal is 2
N
when the length of the transmission sequence is N, and all candidates are processed as stated above. A maximum-likelihood detecting device estimates a candidate of the transmitted signal as a transmitted signal when the square sum provided by the square summing device is smallest.
In case of the maximum-likelihood detection, an operation amount increases in proportion to the exponent of the transmission sequence length N. So the maximum-likelihood detection using a Viterbi algorithm is adopted. The details of the Viterbi algorithm are described in the paper “The Viterbi algorithm”, G. D. Forney, Jr., Proc. IEEE, vol.61, No.3, pp. 268-278, March 1973. In case of the channel model of
FIG. 18
, an error power at a time k can be calculated by knowing transmitted data at the time k and transmitted data at the preceding time (k−2). The maximum-likelihood detection using the Viterbi algorithm uses a figure showing data transition information (hereinafter, referred to as a “trellis diagram”) obtained from the combination of data between two times as shown in FIG.
19
.
In this trellis diagram of
FIG. 19
, the combination of data between two times is connected with a line considering the following characteristic. The characteristic is expressed as follows. For example, if a signal stored in a memory at certain time shows a state “00”, the state transits to any one of a state “10” or a state “00” at a next time, however, it never transits to a state “01” or a state “11”. It is because that when a shift resistor of a state “000” is shifted one time, only “000” or “100” is provided. Accordingly, upon connecting a combination of data between two times with a line, it is assumed that the state “00” and the state “10”, and the state “00” and the state “00” are connected with lines, respectively. However, the state “00” and the state “01”, and the state “00” and the state “11” are not connected with lines, respectively.
In this way, a trellis diagram is formed considering the characteristic of the transition. In
FIG. 19
, a combination connected with a line has a possibility of transition and a combination not connected with a line has no possibility of transition. A line showing the transition of the state is referred to as a branch hereinafter. The trellis diagram has solid lines and dotted lines. The solid line means that a signal
0
is input and the state transits, while the dotted line means that a signal
1
is input and the state transits. A combination of data across three times can be decided by connecting a combination of data between two times with a line as shown in the trellis diagram of FIG.
19
. The error power can be obtained using such a trellis diagram.
Processing of a Viterbi algorithm using such a trellis diagram is explained in detail. When the memory length of the channel is L, the number of states is expressed as 2
L
. In other words, the number of states increases in proportion to exponent of the memory length L of the channel. An operation amount increases corresponding to the number of states. While the sequence estimator of
FIG. 16
searches candidates for all signals, the Viterbi algorithm can decrease the number of processing steps for searching them.
FIG. 20
shows a process of the Viterbi algorithm at each time. Hereinafter,
Kubo Hiroshi
Murakami Keishi
Tanada Kazuo
Birch & Stewart Kolasch & Birch, LLP
Bocure Tesfaldet
Mitsubishi Denki & Kabushiki Kaisha
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