Sequence control apparatus having separate sequence memory and i

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364141, 364189, 36447416, 36447422, G06F 1546

Patent

active

051288575

ABSTRACT:
A sequence control apparatus including a counter which sequentially designates memory areas of a sequence memory to read out respective sets of operation commands to represent respective events of operation of a controllable device. The counter also sequentially designates memory areas of an interlock condition memory to read out respective sets of interlock conditions that should be satisfied for the corresponding events of operation to be performed. When each event of operation is completed, the counter is incremented or decremented, and the conditions of the controllable device are checked to determine whether the set of interlock conditions for the currently designated event of operation are satisfied.

REFERENCES:
patent: 3903515 (1975-09-01), Haydon et al.
patent: 4535456 (1985-08-01), Bauer et al.
patent: 4858102 (1989-08-01), Lovrenich

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