Separation process for silicon-on-insulator wafer fabrication

Details Separation process for silicon-on-insulator wafer fabrication Separation process for silicon-on-insulator wafer fabrication

2000-04-06

2002-05-14

Zarabian, Amir (Department: 2824)

Semiconductor device manufacturing: process

Thinning or removal of substrate

C438S120000

Reexamination Certificate

active

06387829

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of silicon-on-insulator substrates. More particularly, the invention provides a technique for separating (cleaving) a substrate as part of the fabrication process of silicon-on-insulator wafers for semiconductor integrated circuits and microelectromechanical systems.
Delamination of thin films (micron range thickness) from solids such as a single crystal is a processing step that is useful for variety of technologies, including semiconductor processing technology. Prior art includes separation methods as (1) ion cut with thermal initiation (Bruel), (2) ion cut with jet initiation (Henley), and (3) variations of sacrificial layer etching (Gmitter, Yonehara, Kenney).
The separation technique through a hydrogen-rich layer was described by Bruel, U.S. Pat. No. 5,374,564 [1]. This technique is a part of Bruel's process [1] used to fabricate silicon-on-insulator wafers. The technique uses thermal treating of a wafer assembly that includes a hydrogen-implanted wafer. The annealing temperature used is above that at which ion implantation takes place. Typical annealing temperatures are in range from 400 to 500° C. Under annealing the implanted hydrogen begins to diffuse inside of the wafer. Hydrogen coagulates into precipitates that serve as nuclei for subsequent structure transformations. Then flat platelets consisting of hydrogen are formed from the nuclei. The platelets are arranged along <100> silicon crystallographic planes. The platelets have top and bottom silicon <100> surfaces with dangling bonds terminated by hydrogen. Next, bigger platelets continue to grow in expense of smaller platelets according to the Ostvald ripening mechanism. Finally, the continuous hydrogen layer is formed along the plane of the maximum implanted hydrogen. Following annealing, the former single wafer is separated into two thinner wafers.
Another technique to delaminate a top layer from a silicon wafer using the buried hydrogen-rich layer is described by Henley in U.S. Pat. No. 6,013,567 [2]. The wafer is cleaved along the hydrogen-rich plane using a pressurized fluid jet applied initially to the edge of the wafer. The cleavage initiates at the edge due to the jet action and the cleavage wave then propagates through the substrate to release a thin film of material from the substrate.
Still another technique to selectively peel a film from a single crystal is described by Gmitter in U.S. Pat. No. 4,846,931 [3]. The technique is usually referred as epitaxial lift-off. In this technique an epitaxial film is released from a single crystal substrate upon which it is grown. The technique comprises (a) providing a thin release layer (1000 Å) between the film to be grown and the substrate; (b) growing the epitaxial film(s); (c) applying a polymeric support layer which is under tension over the film; and (d) selectively etching the release layer, the tension in the support layer causing the edges of the film to curve upward as the release layer is etched away.
A variation of the epitaxial lift-of process is described by Yamagata in U.S. Pat. No. 5,250,460 [4] and subsequent patents on the ELTRAN process of fabrication of silicon-on-insulator wafers. In this technique the film separation is obtained by etching off a sacrificial layer comprised of porous silicon.
Still another variation of the epitaxial lift-off process for film separation is described by Kenney in U.S. Pat. No. 5,710,057 [5]. In this technique an etchant distribution is facilitated by capillary action in trenches preformed in the seed substrate.
A disadvantage of the Bruel [1] technique is that the roughness of the as-cut surface requires polishing (e.g., CMP) to smooth the surface. This polishing affects the thickness uniformity of the device layer across the wafer. Thus, the polishing process, while improving local roughness, simultaneously increases thickness variations. Another disadvantage of the Bruel process [1] is that the assembly sometimes cleaves along an undesired plane. The desired plane is along the peak density of the implanted hydrogen. The undesirable plane is at a prebonded interface between wafers of the assembly. Defective silicon-on-insulator wafers are the result.
A disadvantage of the epitaxial lift-off technique [3] is that the area of delaminated film is limited to about 1 square inch, that is much less that typical silicon wafer size (4-12 inches in diameter). So the process is not applicable to mainstream semiconductor processing.
A disadvantage of etch-stop based separation techniques [3,4,5] is the difficulty in obtaining a uniform layer thickness for large areas. Since the etchant etches silicon in addition to the sacrificial layer, there is a tendency to reduce the thickness at the thin film silicon near the outer perimeter of the wafer. The result is a separated thin film of decreasing thickness along radii toward the wafer perimeter.
A disadvantage of the side jet technique [2] is that plasma immersion ion implantation dose needed in the process is 10
18
cm
−2
. Such a high dose severely deteriorates the quality of the delaminated layer.
SUMMARY OF THE INVENTION
A technique is detailed for forming a silicon film from a donor silicon substrate with <100> or <111> surface orientations.
A The technique utilizes a step of forming a hydrogen-rich layer in a donor substrate at a selected depth underneath the surface where the hydrogen atoms have a relatively high concentration to define a donor substrate material above the selected depth. The hydrogen-rich layer may be obtained by implanting hydrogen ions through a surface into the donor wafer.
To initiate separation of thus prepared wafer, an energy source is applied to the substrate. The source is selected from the group consisting of ultrasound, hydrostatic pressure, hydrodynamic pressure, infrared light, mechanical, or combination thereof. Said energy source is applied in such a way that energy is deposited preferentially in the hydrogen-rich layer.
The application of said energy source coagulates hydrogen into nuclei having platelet shapes oriented along crystallographic cleavage planes, that is usually the <100> plane. The platelets then form a continuous layer thus releasing the adjacent silicon film.
For said ultrasound and infrared energy cases, choosing preferable parameters means the wavelength is chosen smaller than said donor substrate material thickness (typically less than 10 micrometers).
Advantage of the present invention is the technique adds flexibility for creating customized silicon-on-insulator based microstructures and integrated circuits. Also the technique rises the yield of silicon layer transfer as the hydrogen platelet coagulation along the interface of prebonded silicon wafers is suppressed. Also the technique improves a surface roughness of the silicon-on-insulator wafers obtained.


REFERENCES:
patent: 4846931 (1989-07-01), Gmitter
patent: 5250460 (1993-10-01), Yamagata
patent: 5374564 (1994-12-01), Bruel
patent: 5710057 (1998-01-01), Kenney
patent: 5994207 (1999-11-01), Henley et al.
patent: 6013567 (2000-01-01), Henley
patent: 6221774 (2001-04-01), Malik

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