Separation of a multi-layer integrated circuit device and...

Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing

Reexamination Certificate

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Details

C438S460000, C029S762000

Reexamination Certificate

active

06304792

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multi-layer integrated circuit (IC) devices, and more particularly to package separation of multi-layer IC devices attached at a frontside to the packages.
BACKGROUND OF THE INVENTION
For multi-layer IC devices attached at a frontside to packaging, e.g., oriented in a flip-chip orientation, debugging for defects in the IC is difficult due to having to approach the desired layers from the backside of the device.
FIG. 1
illustrates a sideview block diagram of a typical flip-chip configuration. As shown in
FIG. 1
, an IC device
10
is coupled to a ceramic package
12
(e.g., a C
4
package) via solder bumps
14
. The solder bumps
14
act as chip-to-carrier interconnects to attach the IC device
10
to the ceramic package
12
and to mate with corresponding pad patterns to form the necessary electrical contacts between the circuit(s) of the IC device
10
and pins of the package
12
.
Testing of the circuit remains a challenge due to the upside-down nature of the flip-chip orientation. While the circuit may be approached through the backside layers, such techniques are usually not preferred due to the difficulties associated with having to access the layers in an unconventional order. Further, these techniques normally reduce the thickness of the device to reach the circuit, making the device extremely fragile and cumbersome to handle and utilize during testing.
Accordingly, a need exists for an efficient and effective procedure for separating an IC device from its package to allow utilization, such is testing, from a frontside. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides for device and package separation of a multi-layer integrated circuit device attached at a frontside to an integrated circuit package. In an exemplary method aspect, the method includes cutting through coupling material between the multi-layer integrated circuit and the integrated circuit package with a high precision saw blade. The method further includes cutting with a high precision saw blade of approximately 50 microns thickness. Additionally, the multi-layer integrated circuit device is utilized for device analysis from a frontside following separation from the integrated circuit package by the step of cutting.


REFERENCES:
patent: 4593243 (1986-06-01), Lao et al.
patent: 5708296 (1998-01-01), Bhansali
patent: 5786630 (1998-07-01), Bhansali et al.
patent: 5786701 (1998-07-01), Pedder
patent: 5801432 (1998-09-01), Rostoker et al.
patent: 5886406 (1999-03-01), Bhansali
patent: 5904489 (1999-05-01), Khosropour et al.
patent: 6033288 (1999-05-01), Weisshaus et al.
patent: 6119325 (2000-09-01), Black et al.

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