Separately strained N-channel and P-channel transistors

Details Separately strained N-channel and P-channel transistors Separately strained N-channel and P-channel transistors

2006-05-09

2006-05-09

Wojciechowicz, Edward (Department: 2815)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Subsequent separation into plural bodies

C438S109000

Reexamination Certificate

active

07041576

ABSTRACT:
An integrated circuit with a first plurality of transistors formed on a first wafer and second plurality of transistors formed on a second wafer. At least a substantial majority of the transistor of the first transistor are of a first conductivity type and at least a substantial majority of the transistors of the second plurality are of a second conductivity type. After wafers are bonded together, a portion of the second wafer is removed wherein the strain of the channels of the second plurality of transistors is more compressive than the strain of the channels of the first plurality of transistors.

REFERENCES:
patent: 5534713 (1996-07-01), Ismail
patent: 5872393 (1999-02-01), Sakai et al.
patent: 6059895 (2000-05-01), Chu
patent: 6358828 (2002-03-01), Kadosh
patent: 6500694 (2002-12-01), Enquist
patent: 2003/0231967 (2003-12-01), Najafi et al.
Kwon et al., “A Wafer-Scale 3D IC Technology Platform Using Dielectric Bonding Glues and Copper Damascene Patterned Inter-Wafer Interconnects,” IEEE, pp. 78-80.

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