Separately clocked processor synchronization improvement

Details Separately clocked processor synchronization improvement Separately clocked processor synchronization improvement

1995-06-02

1997-03-18

Auve, Glenn A.

Boots, shoes, and leggings

3951821, 364269, 3642712, 364DIG1, 395733, G06F 1118

Patent

active

056131275

ABSTRACT:
Processor apparatus for control functions performed in a redundant manner utilizing separate clocks but correcting for mismatch in timing thereof by causing an interrupt of the processing through software to a "hold" status to allow time for any lagging processors to catch up before starting a next frame of processing.

REFERENCES:
patent: 3810119 (1974-05-01), Zieve et al.
patent: 4330826 (1982-05-01), Whiteside et al.
patent: 4733353 (1988-03-01), Jaswa
patent: 4937741 (1990-06-01), Harper et al.
patent: 5226152 (1993-07-01), Klug et al.
patent: 5233615 (1994-09-01), Goetz
patent: 5353436 (1994-10-01), Horst
patent: 5384906 (1995-01-01), Horst
The Fifteenth Annual International Symposium on Fault-tolerant Computing, Jun. 19-21, 1985, pp. 246-251, IEEE, NY, U.S.; T. Yoneda et al, "Implementation of Interrupt Handler for Loosely-Synchronized TMR Systems" (see p. 246, right col., line 26--p. 248, right col., line 39, Figs. 1-5).

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