Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-02-23
2000-09-05
Zarabian, A.
Static information storage and retrieval
Addressing
Sync/clocking
36523008, G11C 800
Patent
active
061153206
ABSTRACT:
A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.
REFERENCES:
patent: 4882709 (1989-11-01), Wyland
patent: 5515325 (1996-05-01), Wada
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5546344 (1996-08-01), Fawcett
patent: 5568430 (1996-10-01), Ting
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5617362 (1997-04-01), Mori et al.
patent: 5644729 (1997-07-01), Amini et al.
patent: 5652724 (1997-07-01), Manning
patent: 5659696 (1997-08-01), Amini et al.
patent: 5663901 (1997-09-01), Wallace et al.
patent: 5675549 (1997-10-01), Ong et al.
patent: 5699317 (1997-12-01), Sartore et al.
patent: 5828606 (1998-10-01), Mick
patent: 5838631 (1998-11-01), Mick
patent: 5841732 (1998-11-01), Mick
patent: 5875151 (1999-02-01), Mick
Prince, Betty, Semiconductor Memories, Second Edition, 467-472 (John Wiley & Sons ed., 1991) (1983).
Baumann Mark W.
Mick John R.
Integrated Device Technology Inc.
Zarabian A.
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