Sensitive high speed clocked comparator

Details Sensitive high speed clocked comparator Sensitive high speed clocked comparator

1978-02-14

1979-04-03

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307DIG3, 328146, H03K 520

Patent

active

041479432

ABSTRACT:
A sensitive high speed clocked comparator for use with low level differential logic circuits which utilizes an amplifier, a Gilbert Gain Cell, and load devices to amplify the difference between analog voltages being compared, and a high speed latch to increase the output voltage level of the Gain Cell up to the level of logic signals used in low level differential logic circuits. The circuit has two modes, a "follow" mode wherein the amplifier and Gilbert Gain Cell cause an unbalance in the currents through two load devices responsive to any difference in input voltage, and a "latch" mode wherein a latch causes the current unbalance to increase and to latch. The modes are sequentially selected by clocking.

REFERENCES:
patent: 3621301 (1971-11-01), Tomczak
J. E. Gersbach, "Surefire Latch", IBM Technical Disclosure Bulletin, vol. 18, No. 1, Jun. 1975, p. 73.

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