Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-24
2002-12-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185290
Reexamination Certificate
active
06490203
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to non-volatile memory devices having a floating gate . More particularly, the present invention relates to a new and novel reading circuitry and method for performing program verify, erase verify and over-erase-correction verify operations on a selected memory core cell in an array of EPROM, EEPROM, or Flash EEPROM memory core cells which uses only a single reference cell so as to reduce the amount of trimming time required during manufacturing.
2. Description of the Prior Art
As is generally well-known in the art, non-volatile memory devices using a floating gate for the storage of charges thereon such as EPROMs (electrically programmable read-only memories), EEFROMs (electrically, erasable programmable read only memories) or Flash EEPROMs have emerged in recent years. In such a conventional Flash EEPROM memory device, a plurality of such one-transistor memory may be formed on a P-type semiconductor substrate in which each cell is comprised of an n
+
drain region and an n
+
source region both formed integrally within the substrate. A relatively thin gate dielectric layer is interposed between a top surface of the substrate and a conductive polysilicon floating gate. A polysilicon control gate is insulatively supported above the floating gate by a second dielectric layer. A channel region in the substrate separates the drain and source regions.
As is well-known, the charge of the floating gate of the one-transistor cell is dependent upon the number of electrons contained in the floating gate. During the programming mode, electrons are added to the floating gate of the cell so as to increase its threshold voltage. The term “threshold” refers to a gate-to-source voltage that must be applied between the gate and the source of the cell in order to cause it to conduct. During the erase mode, electrons are removed from the floating gate of the cell so as to decrease its threshold voltage. In programmed state, the threshold voltage of a cell is typically set at greater than +6.5 volts, while the threshold voltage of a cell in an erased state is typically limited below +3.0 volts.
In order to determine whether the cell has been programmed or not, the cell is read by applying a small positive voltage to the control gate between the +3.0 and +6.5 volt range, typically +5.0 volts, with the source region held at a ground potential (0 volts) and the drain held at a potential between +1 to +2 volts. If the transistor cell conducts or is turned-on, a current will flow through the transistor representing a “1” bit or erased state. On the other hand, if the transistor cell does not conduct or is turned-off no current will flow through the transistor representing a “” bit or programmed state.
FIG. 1
is a simplified functional block diagram of a conventional semiconductor integrated memory circuit device
100
which includes a Flash EEPROM memory array
102
formed of a plurality of memory core cells MC
11
-NCnm (each being formed as described above). The plurality of memory cells NC
11
-MCnm are arranged in an n×m matrix on a single integrated circuit chip. Each of the memory cells is comprised of one of the array core transistors Q
P11
through Q
Pnm
which function as a memory transistor for storing data “1” or “” therein. Each of the core transistors has its drain connected to one of the plurality of bit lines BL-BLM. All of the sources of the array core transistors are connected to a common array ground potential VSS. Each of the core transistors also has its control gate connected to one of the plurality of word lines WL-WLN.
The memory circuit device
100
further includes a row address decoder
104
, a column address decoder
106
, and a Y-pass gate circuit
108
. The row address decoder
104
selects one of the corresponding word lines WL-WLn in the memory core cell array
102
in response to row address signals A
i
. At the same time, the column decoder
106
selects one of the corresponding bit lines Bl-BLm in response to column address signals A
j
. The Y-pass gate circuit
108
connects the corresponding array bit lines to a sensing or reading circuitry
110
.
In order to determine the state of a selected memory core cell, the reading circuitry
110
includes a sense amplifier functioning as a comparator which receives a core current signal from a bit line on its one input and receives a reference current signal from a reference line on its other input. In this manner, the core current signal corresponding to a core current is compared with the reference current signal corresponding to a reference current from a reference cell. The result on the output of the comparator indicates whether the selected memory core cell is storing a “1” or “0”.
With reference to
FIG. 2
of the drawings, there is shown a simplified schematic circuit diagram of certain portions of the memory circuit device
100
of
FIG. 1
to explain how the program verify, erase verify, and over-erase-correction verify states of one selected array core transistor Q
P
is determined. In particular, the reading or sensing circuitry
110
of
FIG. 2
includes a comparator
120
, a reference resistor
122
having a resistance value R
2
, a sense resistor
124
having a resistance value R
1
, a core transistor Q
P
, and a plurality of reference transistors Q
R1
-Q
R4
. The comparator
120
is actually one of the sense amplifiers of FIG.
1
.
The reference resistor
122
has its one end connected to a supply potential or voltage VCC, which is typically at +1.0 volts, and its other end connected to the non-inverting input of the comparator
120
at node A. The node A is also coupled to the drains of the reference transistors Q
R1
-Q
R4
via the reference cell line REF and corresponding switches S
1
-S
4
. One end of the sense resistor
124
is also connected to the supply potential VCC, and the other end thereof is connected to the inverting input of the comparator
120
at node B. The node B is also connected to the drain of the core transistor Q
P
via the selected bit line BL. As can be seen, the gates of the core transistor Q
P
and the reference transistors Q
R1
-Q
R4
are connected together and receive the same control gate voltage VG_SENSE via the selected word line WL.
During a normal Read mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell Q
P
is compared with the reference current IREF from the reference cell Q
R1
having a read threshold voltage RD_VT by closing the switch S
1
. During a program verify mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell Q
P
is compared with the reference current IREF from the reference cell Q
R2
having a program verify threshold voltage PGM_VT by closing the switch S
2
. During an erase-verify mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell Q
P
is compared with the reference current IREF from the reference cell Q
R3
having an erase-verify threshold voltage ERS_VT by closing the switch S
3
. During an over-erase-correction mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell Q
P
is compared with the reference current IREF from the reference cell Q
R4
having an over-erase-correction threshold voltage OEC_VT by closing the switch S
4
.
The various threshold voltages for the four reference cells Q
R1
-Q
R4
are required to satisfy the following condition:
OEC_VT<
ERS
—
VT<RD
—
VT<PGM
—
VT
As will be noted from
FIG. 3
, the reference cell current from the four respective reference cells Q
R1
-Q
R4
(each having a different reference threshold voltage) are plotted as a function of the control gate bias V
G
applied to the respective reference cells. Since the reference cells are identical to the array core cells
Chin Davis
EDN Silicon Devices, Inc.
Le Thong
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