Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-11-05
2004-04-06
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185200, C365S185210, C365S185330
Reexamination Certificate
active
06717848
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a sensing circuit in a multi-level flash memory cell. More particularly, the invention relates to a sensing circuit in a multi-level flash memory cell capable of exactly sensing a state of the multi-level flash memory cell by sensing four states of the multi-level flash memory cell based on first through third reference cells, in which the first reference cell has a threshold voltage by which a program or erase state of a floating gate can be determined in a state that a capacitor of the multi-level flash memory cell is discharged, a second reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a discharge state, and a third reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a program state.
2. Description of the Prior Art
In order to store large amount of information, a multi-level flash memory cell is constructed in which a capacitor using a ferroelectric material as a dielectric film is connected to a source of a flash memory cell. A cross-sectional view of the multi-level flash memory cell is shown in FIG.
1
. In FIG.
1
. the reference characters V
S
, V
D
, and V
G
are voltages applied to a source, a drain and a gate of the flash memory cell, respectively, and VB_P and VB_N are charge voltages stored respectively in a P-type well and an N-type well of the capacitor.
A N-well
102
and a P-well
103
are formed on a semiconductor substrate
101
. A stack gate structure in which a tunnel oxide film
104
, a floating gate
105
, a first dielectric film
106
and a control gate
107
are stacked at a given region on the semiconductor substrate
101
is formed. A source
108
and a drain
109
are formed at a given region of the semiconductor substrate
101
by an impurity ion implantation process. A given region of a first interlayer insulating film
110
formed on the entire structure is etched to form a first contact hole through which the source
108
and the drain
109
are exposed. A conductive material is filled up to form a plug
111
. A bit line
112
to be connected to the drain
109
and a pad
113
to be connected to the source
108
is formed, on an upper side of the first interlayer insulating film
110
. A given region of the second interlayer insulating film
114
formed on the entire structure is etched to form a second contact hole through which the pad
113
is exposed. A lower electrode
115
is formed so that the second contact hole can be buried. A second dielectric film
116
and an upper electrode
117
are formed on the lower electrode
115
. At this time, the second dielectric film
116
is made of a ferroelectric material such as PZT, etc. other than common materials so that information can be maintained with supply of the power stopped.
As such, the capacitor is constructed using a ferroelectric material as a dielectric film so that the capacitor can be connected to a source of the flash memory cell. Therefore, information of 2 bits per cell can be stored by combination of whether the floating gate is charged and the capacitor is charged.
Table 1 shows a state of the multi-level flash memory cell depending on a state of the floating gate and whether the capacitor is charged.
In other words, if the floating gate is a program state and the capacitor is charged, the cell has a state of “00”. If the floating gate is at a program state and the capacitor is not charged, the cell has a state of “01”. Also, if the floating gate is at an erase state and the capacitor is charged, the cell has a state of “10”. If the floating gate is at an erase state and the capacitor is not charged, the cell has a state of “11”.
TABLE 1
State of Floating
Capacitor
Gate
Charged?
Cell State
Program: ″−″
Yes : ″0″
″00″
No : ″1″
″01″
Erase: ″+″
Yes : ″0″
″10″
No : ″1″
″11″
However, it is not clearly defined on how the information store state of the above cell can be determined. Further, there is a problem that the procedure of determining the state is very complicated.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a sensing circuit in a multi-level flash memory cell capable of exactly determining a state of the multi-level flash memory cell having a flash memory cell and a capacitor connected to a source of the flash memory cell.
In order to accomplish the above object, a sensing circuit in a multi-level flash memory cell according to the present invention, is characterized in that it comprises a multi-level flash memory cell having a flash memory cell and a capacitor connected to a source of the flash memory cell; a first sense amplifier for comparing a state of the multi-level flash memory cell with a first reference cell; a second sense amplifier for comparing a state of the multi-level flash memory cell with a second reference cell; a third sense amplifier for comparing a state of the multi-level flash memory cell with a third reference cell; a logical means for logically combining a sensing enable signal and an output signal of the first sense amplifier; first and second switching means for supplying the power supply voltage, respectively, depending on an output signal of the logical means and its inverted signal; a third switching means for connecting the second reference cell and the multi-level flash memory cell to the second sense amplifier, depending on the power supply voltage supplied by the first switching means; and a fourth switching means for connecting the third reference cell and the multi-level flash memory cell to the third sense amplifier, depending on the power supply voltage supplied by the second switching means.
Meanwhile, a first reference cell has a threshold voltage by which a program or erase state of a floating gate can be determined in a state that a capacitor of the multi-level flash memory cell having a source connected to a capacitor and a flash memory cell are discharged, a second reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a discharge state, and a third reference cell has a threshold voltage by which a charge or discharge,state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a program state.
REFERENCES:
patent: 5485422 (1996-01-01), Bauer et al.
patent: 5646887 (1997-07-01), Truong et al.
patent: 5877985 (1999-03-01), Banba et al.
patent: 6018477 (2000-01-01), Wang
patent: 6222762 (2001-04-01), Guterman et al.
Choi Won Yeol
Jeon Yoo Nam
Kim Ki Seog
You Young Seon
Holman PLLC Jacobson
Hynix / Semiconductor Inc.
Phan Trong
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