Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-28
2004-03-09
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S205000, C365S207000, C365S208000
Reexamination Certificate
active
06704225
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a sensing circuit for a nonvolatile memory device for preventing gate oxide breakdown and for increasing the processing speed of a memory device.
DESCRIPTION OF THE PRIOR ARTS
FIG. 1
is a circuit diagram of a conventional sensing circuit of a flash memory device.
Referring to
FIG. 1
, a first PMOS transistor P
11
and a second PMOS transistor P
12
are provided between a power source and node Q
11
and they are connected to each other in series. The first PMOS transistor P
11
is driven by a sensing amplifier enable bar signal SAENb and the second PMOS transistor P
12
is driven by the electric potential at node Q
13
. A drain of a first NMOS transistor N
11
is connected to node Q
11
and its source is connected to ground V
SS
. A drain of a second NMOS transistor N
12
is connected to node Q
11
and its source is connected to ground V
SS
. The first and second NMOS transistors N
11
and N
12
are commonly connected at node Q
11
. The first NMOS transistor N
11
is driven by the sensing amplifier enable bar signal SAENb and the second NMOS transistor N
12
is driven by the electric potential at node Q
13
. A third PMOS transistor P
13
is connected to a third NMOS transistor N
13
in parallel and they are provided between a power source and node Q
12
. The third PMOS transistor P
13
is turned on due to a ground voltage and the third NMOS transistor N
13
is turned on due to a power voltage V
cc
. A fourth NMOS transistor N
14
is connected to node Q
12
and to node Q
13
. The fourth NMOS transistor N
14
is driven by the electric potential at node Q
11
. A fifth NMOS transistor N
15
is connected to node Q
13
and to a program enable signal PGMEN, driven by the program enable signal PGMEN. A sixth NMOS transistor N
16
and a seventh NMOS transistor N
17
are connected in series to each other between node Q
13
and the ground V
SS
. The sixth NMOS transistor N
16
is driven by a first address signal ADDR
1
and the seventh NMOS transistor N
17
is driven by a second address signal ADDR
2
. A memory cell array M
11
is connected to the seventh NMOS transistor and a sense amplifier
11
receives the electric potential at node Q
12
, compares it with a reference cell voltage Vref and outputs sensing signal SAOUT.
The method of driving the above-mentioned flash memory device is described below in detail with reference to FIG.
2
.
At a first time period T
1
, a sensing amplifier enable bar signal SAENb is applied to the first PMOS transistor P
11
and the first NMOS transistor N
11
in a low state. Thus, the first PMOS transistor P
11
is turned on and the first NMOS transistor N
11
is turned off. The second PMOS transistor P
12
is turned on by the turned on first PMOS transistor P
11
or an electric potential at node Q
13
, which is maintained at an initial low state. The power voltage V
cc
is applied through the second PMOS transistor P
12
to node Q
11
and it is maintained at a high state. The fourth NMOS transistor N
14
is turned on by an electric potential at node Q
11
, which is maintained at a high state. Node Q
13
is in a high state due to the power voltage V
cc
applied from the third PMOS transistor P
13
, the third NMOS transistor N
13
, and the fourth NMOS transistor N
14
. However, since the first address signal and the second address signal stays in a low state, the sixth and seventh transistors N
16
and N
17
can not be turned on so a current path of a memory cell array M
11
also can not be established. Therefore, node Q
13
stays in a high state. In response to its potential, the second PMOS transistor P
12
is turned off and the second NMOS transistor N
12
is turned on. As the second NMOS transistor N
12
is turned on, the potential at node Q
11
becomes low. Therefore, as a result of the above-mentioned operations of the conventional sensing circuit, the conventional sensing circuit maintains a constant potential at node Q
13
in spite of increasing the power voltage V
cc
. Node Q
11
also has a constant regulated potential.
At a second time period T
2
, high levels of the first and second address signals ADDR
1
and ADDR
2
are respectively applied to the sixth and seventh NMOS transistors N
16
and N
17
. However, node Q
13
is still maintained at a constant potential because a high enough wordline voltage WL is not applied for turning on the memory cell array M
11
.
At a third time period T
3
, a high voltage level on the wordline WL is applied to the memory cell array (non-volatile transistor) M
11
, so that a current path is established in the memory cell array M
11
. In other words, in the case that the memory cell array M
11
is programmed, the potential at node Q
13
is maintained at a constant level because a current does not flow through the cell and the value of the potential at a sensing node Q
12
is the difference between the power voltage V
cc
and a threshold voltage on the third PMOS transistor P
13
or the third NMOS transistor N
13
. In the case that data in the memory cell array M
11
is erased, the current flows through the cell, therefore, the voltage on node Q
12
is lower than in the case that the memory cell array M
11
is programmed. In other words, the conventional sense amplifier
11
determines a sensing result by comparing the voltage at node Q
12
with a reference voltage Vref. The voltage at node Q
12
is regulated according to whether the memory cell array M
11
is programmed or erased.
There are several requirements for driving the conventional sensing circuit of the volatile memory device normally. First of all, the breakdown voltage has to be high since the oxide film has to be thin in order to drive the sensing circuit with a low voltage. Second, the transconductance has to be high for quickly pre-charging a high load voltage on a bit line. Finally, the threshold of the fourth NMOS transistor N
14
has to be set up efficiently for controlling the potential at node Q
12
. The fourth NMOS transistor N
14
is driven by a potential at node Q
13
and a potential at node Q
12
is controlled by driving the fourth NMOS transistor N
14
. These elements of the circuit are formed as a negative feedback loop. This is because the response time may be longer if the voltage swing of node Q
11
is too great in the case that a depletion MOS transistor is used as the NMOS transistors in the circuit.
The conventional sensing circuit of the nonvolatile memory device uses the fourth NMOS transistor N
14
as a voltage NMOS transistor for controlling the potential on node Q
12
. The low voltage of NMOS transistor is 0.55 V for the threshold voltage and 4 V for the breakdown voltage. However, the time for pre-charging a bit line, in this case, may be longer since the transconductance is small. Additionally, since the gate used for low voltage driving employs a thin oxide film of approximately 80 Å, the oxide film can be easily broken down while the circuit is being driven.
Meanwhile, a low voltage depletion NMOS transistor can be used for the fourth NMOS transistor N
14
. The low voltage depletion NMOS transistor has a threshold voltage of 0 V and a breakdown voltage of 4 V. In this case, the transconductance is high enough to result in a decrease in the length of an initial bit line pre-charge process. However, after the bit line pre-charge process is done, the fourth NMOS transistor N
14
is turned off since the potential on node Q
11
is higher than the potential at node Q
13
. The fourth NMOS transistor N
14
is turned on when the potential at node Q
13
is equal to or higher to the potential at node Q
11
. Therefore, additional time is required for the above-mentioned process and that is the reason why the processing time of a memory should be reduced.
The above-mentioned problem of using a low voltage NMOS transistor or depletion NMOS transistor in the conventional sensing circuit could be solved by installing an additional circuit; however, it reduces sensing time, reduces stability of a memory cell, and increase the size of the circuit.
SUMMARY OF THE INVENTION
It is,
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Yoha Connie C.
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