Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-06-14
2003-03-18
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S210130, C365S189090
Reexamination Certificate
active
06535428
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to the field of semiconductor memories, particularly but not limitatively to non-volatile memories such as ROMs, EPROMs, EEPROMs and Flash EPROMs or EEPROMs. More specifically, the invention concerns a sensing circuit for sensing the information stored in memory cells, and more particularly to a sensing circuit adapted to the sensing of multi-level memory cells programmable in more than two programming states for storing more than one bit of information.
BACKGROUND OF THE INVENTION
In non-volatile semiconductor memories such as EPROMs, EEPROMs and Flash EPROMs or EEPROMs, the information is stored as a charge trapped in a floating gate electrode of a floating-gate MOS transistor memory cell. One bit of information can be stored by means of two different charge values, which correspond to two different values or levels of the MOS transistor threshold voltage.
In order to sense the single bit of information stored in a memory cell, the latter is biased in a prescribed sense condition and the current sunk by the memory cell is detected, normally by comparison with a reference current. The memory cell sense condition is chosen so that, depending on the charge trapped in the floating gate, the memory cell either conducts a current or does not conduct any current.
In recent years the possibility of storing more than one bit of information in each memory cell has been proposed. More than one bit of information can be stored in a memory cell provided that the number of possible charge values trapped in the floating gate electrode is increased. This corresponds to increasing the number of different possible threshold voltage levels of the memory cell. The memory cell is therefore referred to as multi-level, in contrast to the two-level memory cell in which only two threshold voltage levels exist.
For example, a four-level memory cell stores two bits of information, while a sixteen-level memory cell stores four bits of information.
Memory devices with multi-level memory cells substantially increase the storage capacity per unit area.
The introduction of multi-level memory cells has led to the implementation of sensing circuits that attempt to maximally exploit the memory cell operating window. The control gate electrode of the memory cell is thus biased at the maximum potential allowed by the fabrication technology, compatibly with the performance required of the memory device in terms of retention of the stored data. Nowadays, the typical sense potential applied to the memory cell control gate electrode is approximately 6 V.
Additionally, the necessity of allocating several different threshold voltage levels, for example four or even sixteen, leads to the maximum distribution thereof between the minimum and maximum threshold voltage levels which can be detected by the sensing circuit.
Clearly, for low threshold voltage levels the memory cell sinks relatively high currents, while for threshold voltage levels close to the maximum detectable value the current sunk by the memory cell is very small and becomes zero for the highest threshold voltage level.
As a consequence, the biasing conditions of the sensing circuits significantly changes in dependence of the status of the memory cell to be sensed, that is of the memory cell threshold voltage.
The changes in the biasing conditions of the sensing circuits may be unacceptable in terms of the different length of the transients, which causes different access times depending on the fact that the accessed memory cell has a low or high threshold voltage level.
Additionally, the biasing condition of the memory cell, particularly the bias voltage of the drain electrode of the floating-gate MOS transistor, varies in dependence of the memory cell programming state: for low threshold voltage levels, corresponding to relatively high currents sunk by the memory cell, the drain voltage lowers, while for high threshold voltage levels, corresponding to low currents, the drain voltage rises. These changes in the drain biasing condition may attenuate the signal to be detected in a non-linear way.
SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention provide a sensing circuit structurally and functionally adapted to overcome the drawbacks of the prior-art circuits.
According to a first aspect of the present invention, a sensing circuit for sensing a memory cell is provided. The sensing circuit comprises a first circuit branch electrically connectable to the memory cell so as to be run through by a memory cell current. The first circuit branch includes at least one first transistor which, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.
In one embodiment, the bias current generator comprises a first current injector for injecting a first current into a first electrode of the first transistor, and a first current extractor for extracting a second current from a second electrode of the first transistor.
Advantageously, the first current extractor comprises a first two-branch current-mirror circuit with a first current-mirror circuit branch run through by a predetermined current, a second current-mirror circuit branch sinking the second current, and an operational amplifier for controlling a conductivity of the second current-mirror circuit branch so as to keep the second current at a prescribed value, fixed by the predetermined current.
According to another aspect of the present invention, there is provided a current extractor circuit for extracting a prescribed current from a circuit node. The current extractor circuit comprises a two-branch current-mirror circuit with a first current-mirror circuit branch run through by a predetermined current, a second current-mirror circuit branch for extracting the prescribed current, and an operational amplifier for controlling a conductivity of the second current-mirror circuit branch so as to keep the second current at a prescribed value, fixed by the predetermined current.
REFERENCES:
patent: 6292398 (2001-09-01), Pasotti et al.
patent: 6400607 (2002-06-01), Pasotti et al.
De Sandre Guido
Guaitini Giovanni
Iezzi David
Pasotti Marco
Poles Marco
Jorgenson Lisa K.
Le Vu A.
STMicroelectronics S.r.l.
Tarleton E. Russell
LandOfFree
Sensing circuit for memory cells does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sensing circuit for memory cells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sensing circuit for memory cells will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3002598