Sensing circuit for memory cells

Details Sensing circuit for memory cells Sensing circuit for memory cells

1976-08-09

1978-01-24

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307238, 307279, 307DIG3, 365203, 365205, H03K 520, H03K 518, H03K 3286, G11C 1140

Patent

active

040705900

ABSTRACT:
A weak signal detecting circuit in which a sensing circuit formed with a flip-flop circuit, and bit lines each having connected thereto a plurality of 1-transistor type memory cells, are interconnected by separation transistors for separating them from each other, and in which power supply transistors are inserted between power sources and the bit lines. When the power supply transistors are turned on, the separation transistors are turned off, so that a signal detection can be performed with little power consumption. Further, in such a case, the bit lines are disconnected from the sensing circuit to thereby enable a high-speed and highly sensitive detecting operation to be stably achieved regardless of the number of memory cells.

REFERENCES:
patent: 3774176 (1973-11-01), Stein et al.
patent: 3838295 (1974-09-01), Lindell
patent: 3892984 (1975-07-01), Stein
patent: 3940747 (1976-02-01), Kud et al.
patent: 3959781 (1976-05-01), Mehta et al.
patent: 3973139 (1976-08-01), Dingwall
patent: 3993917 (1976-11-01), Kalter
Furman et al., "Sense Latch Circuit for Memory Cells"; IBM Tech. Discl. Bull.; vol. 16, No. 9, pp. 2792-2793, 2/1974.

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