Sensing and logic for multiple bit per cell ROM

Details Sensing and logic for multiple bit per cell ROM Sensing and logic for multiple bit per cell ROM

1982-08-16

1984-12-11

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307360, 307363, 324 57R, H03K 524, H03K 5153

Patent

active

044880650

ABSTRACT:
A sensing circuit for determining the amplitude of an unknown impedance by comparing the voltage levels generated in a succession of current mirror circuits. In one form, the present circuit is connected to a ROM array comprised of FET devices having the potential of 2.sup.n different channel structures, impedances, to represent n different bits of data. When addressed, the selected ROM FET is coupled to a current mirror reference FET, whose commonly connected gate and drain electrodes are further coupled to a succession of 2.sup.n -1 current mirror FETs. Each of the current mirror FETs is connected in conductive series with an incrementally different impedance, the value of each impedance lying substantially midway between the 2.sup.n potential impedances possible in the ROM cell FET. The voltages on the current mirror FETs are individually compared to the voltage on the current mirror reference FET to generate a digital format representation of the relative magnitudes. The n data bits in the addressed ROM cell are then decoded by digital logic blocks.

REFERENCES:
patent: 3979606 (1976-09-01), Ahmed
patent: 4047059 (1977-09-01), Rosenthal
patent: 4069431 (1978-01-01), Kucharewski
patent: 4142118 (1979-02-01), Guritz
patent: 4192014 (1980-03-01), Craycraft
R. E. Myrick, (Mostek Corp.), "Multi-Bit Read Only Memory Cell Sensing Circuit", International Publication No. WO82/02276, Jul. 8, 1982.
M. Stark, "Two Bits Per Cell ROM", 1981 IEEE, pp. 209-212.
I. A. Young, "A High-Performance All-Enchancement NMOS Operational Amplifier", IEEE J. Solid-State Circuits, vol. SC-14, No. 6, pp. 1070-1077, Dec. 1979.
Y. P. Tsividis, D. L. Fraser, and J. E. Dziak, "A Process-Insensitive High-Performance NMOS Operational Amplifier, IEEE J. Solid-State Circuits, vol. SC-15, No. 6, pp. 921-928, Dec. 1980.
John G. Posa, "Four-State Cell Doubles ROM Bit Capacity", Electronics, Oct. 9, 1980.
J. Robert Lineback, "Four-State Cell Called Density Key", Electronics, Jun. 30, 1982.

Affiliated with

Also associated with

Rating

Sensing and logic for multiple bit per cell ROM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sensing and logic for multiple bit per cell ROM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sensing and logic for multiple bit per cell ROM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1465507