Sense-write circuit for random access memory

Details Sense-write circuit for random access memory Sense-write circuit for random access memory

1976-11-26

1978-07-04

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 307350, 307DIG3, 365155, 365189, 365208, G11C 700, G11C 1140, H03K 3286, H03K 3353

Patent

active

040990702

ABSTRACT:
A sense-write circuit for use with a emitter coupled logic memory array is provided. A first differential stage includes a pair of emitter-coupled transistors connected to a current source controlled by a chip select voltage. A first one of the emitter-coupled transistors has its base connected to a first reference voltage and the second one of said transistors has its base coupled to a write enable input. The collector of a first one of the emitter-coupled transistors serves as a current source for a second differential stage including a second pair of emitter-coupled transistors, a first one having its base connected to a second reference voltage and the second having its base coupled to a data input conductor. The two respective outputs of the second differential stage are coupled to emitter follower drivers, and are also independently coupled through a pair of respective diode-connected transistors to the collector of the first transistor of the first emitter coupled pair.

REFERENCES:
patent: 3538348 (1970-11-01), Hillis et al.
patent: 3676704 (1972-07-01), Donofrio et al.
patent: 3700915 (1972-10-01), Marley
patent: 3713115 (1973-01-01), Duben
patent: 3736574 (1973-05-01), Gersbach
patent: 3919566 (1975-11-01), Millhollan et al.
Davis et al., "Associative-Memory System Using Latchable Search Drivers," IBM Tech. Discl. Bull.; vol. 15, No. 3, pp. 719-720; 8/1972.

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