Sense latch circuit for a bisectional memory array

Details Sense latch circuit for a bisectional memory array Sense latch circuit for a bisectional memory array

1976-04-27

1977-10-18

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

307238, 340173FF, G11C 502, G11C 706

Patent

active

040548651

ABSTRACT:
A memory circuit includes a plurality of memory cells arranged in an array of intersecting rows and columns and a plurality of differential amplifiers corresponding to the number of columns in the array. The memory array is divided into first and second row groups. Each of the differential amplifiers has one input connected to the memory cells in one of the row groups in one of the columns, and a second input connected to the memory cells in the second row group and to the same column connected to the first input. An output sense amplifier has one input selectively connected to the first input of a selected differential amplifier, and a second input selectively connected to a second input of the selected differential amplifier.

REFERENCES:
patent: 3714638 (1973-01-01), Dingwall et al.
patent: 3838295 (1974-09-01), Lindell
patent: 4003035 (1977-01-01), Hoffman et al.
patent: 4004285 (1977-01-01), Bormann et al.

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