Sense circuit for an MNOS array using a pair of CMOS inverters c

Details Sense circuit for an MNOS array using a pair of CMOS inverters c Sense circuit for an MNOS array using a pair of CMOS inverters c

1977-05-12

1978-06-20

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307238, 307279, 307288, 307362, 307DIG3, 365184, 365205, H03K 520, H03K 3286, G11C 700, G11C 1134

Patent

active

040964019

ABSTRACT:
The sense circuit includes first and second inverters, connected at their inputs to first and second nodes, respectively. The inverters are selectively cross-coupled by means of transmission gates whose conduction paths are connected between the output of the first and second inverters, respectively, and the inputs of the second and first inverters, respectively. The control electrodes of the transmission gates are coupled to the first and second nodes whereby the transmission gates are turned on and off in response to the voltage levels at the first and second nodes. In the operation of the circuit a precharge voltage, having a polarity and magnitude to turn off the transmission gates, is applied to the two nodes. Subsequently, first and second current signals, having a polarity to generate potentials to turn on the transmission gates, are applied to the first and second nodes, respectively, altering the potentials at the nodes until the transmission gates are turned on. The two inverters are then cross-coupled and latch to either one of two states depending on the difference in the voltage levels at the two nodes. Unlike previously known sense circuits, the need for clock signals to control the conduction at the cross-coupling transmission gates is avoided, since the signals for controlling the conduction of these transmission gates are derived from points within the sense amplifier itself.

REFERENCES:
patent: 3849673 (1974-11-01), Koo
patent: 3868656 (1975-02-01), Stein et al.
patent: 3895360 (1975-07-01), Cricchi
patent: 3983545 (1976-09-01), Cordaro
patent: 3992704 (1976-11-01), Kantz
Chin et al., "Sense Latch for One-Device Memory Cell", IBM Tech. Discl. Bull.; vol. 15, No. 11, pp. 3379-3380, 4/1973.
Chu et al., "Low-Power, High-Speed Sense Latch", IBM Tech. Discl. Bull.; vol. 17, No. 9, pp. 2582-2583, 2/1975.

Affiliated with

Also associated with

Rating

Sense circuit for an MNOS array using a pair of CMOS inverters c does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sense circuit for an MNOS array using a pair of CMOS inverters c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sense circuit for an MNOS array using a pair of CMOS inverters c will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1136204