Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-03-25
2001-02-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S205000, C365S185030, C365S185200
Reexamination Certificate
active
06191977
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sense circuit of a flash memory device and, in particular, to a sense circuit of a flash memory device which sense, according to a clock signal having a constant period and a plurality of control signal, data on a flash memory cell capable of storing multi-level, and transforms it to binary data.
2. Related Prior Art
In general, in case of sensing information stored in a memory cell, sensing is done by comparing an amount of current flowing through the memory cell and that flowing through the reference memory cell.
A conventional memory cell is designed to store only one data and also a sense amplifier sensing such cell is designed to sense only one data. However, there is a problem in that storing only one data to one cell requires a plurality of memory cells in proportion to the amount of data and degrades the high-density integration of a device. To solve such problem, a memory cell which can store multi-level is developed. Accordingly, the memory cell has become to be able to store one or more data, and development of a sense amplifier which can precisely sense data stored in such cell has become necessary.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a sense circuit of a flash memory device which can sense, according to a clock signal having a constant period and a plurality of control signals, data on a flash memory cell capable of storing multilevel, trans form it to binary data.
A sense circuit according to the present invention to accomplish the above described object comprises a control signal generator for generating a plurality of voltage control signals, a clock signal having constant period and a plurality of control pulses according to a sense amplifier enable signal, a control voltage generator for generating multi-steps voltage according to the clock signal and the plurality of voltage control signals, sequentially supplying the multi-steps voltage to a program gate of the memory cell, generating a reference voltage according to the sense amplifier enable signal and supplying the reference voltage to a program gate of a reference cell; and a sense amplifier for sequentially comparing a plurality of data stored in the memory cell and a data of the reference cell, storing the result according to the control pulse and converting it into binary data.
REFERENCES:
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5687114 (1997-11-01), Khan
patent: 5729490 (1998-03-01), Calligaro et al.
patent: 5768187 (1998-06-01), Uchino et al.
patent: 5768188 (1998-06-01), Park et al.
patent: 5768193 (1998-06-01), Lee et al.
patent: 5796667 (1998-08-01), Sweha et al.
patent: 5815443 (1998-09-01), Sweha et al.
patent: 5822256 (1998-10-01), Bauer et al.
patent: 5828601 (1998-10-01), Hollmer et al.
patent: 5828616 (1998-10-01), Bauer et al.
patent: 06162787 (1992-11-01), None
patent: 06176585 (1992-12-01), None
patent: 06215585 (1993-01-01), None
patent: 06251593 (1993-02-01), None
patent: 10093054 (1996-09-01), None
patent: 10228784 (1997-02-01), None
Elms Richard
Hyundai Electronics Industries Co,. Ltd.
Nguyen Tuan T.
Pennie & Edmonds LLP
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