Sense and hold amplifier

Details Sense and hold amplifier Sense and hold amplifier

1995-03-31

1996-06-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 51, 327 57, 327198, H03F 345

Patent

active

055281788

ABSTRACT:
A SRCMOS sense amplifier is provided with a latch in the output stage. When a sense amplifier input signal propagates through the circuit and reaches the output stage, a reset signal is generated resetting and charging the input stage and an enable buffer stage of the amplifier to allow the input stage to begin receiving new data while previous data is latched in the output stage. An output stage reset enable is generated when data is at the output terminals of the output stage. The reset enable is combined with a clock signal in a separate output stage reset circuit to reset the circuit on a clocked basis. A further input to the output stage reset circuit is a feedback from a next circuit stage indicating that the data has been properly received in the next stage. The output stage may be reset either in response to the feedback signal from the next stage or in the presence of the reset enable and the clock signal.

REFERENCES:
patent: 5140199 (1992-08-01), Seo
patent: 5297092 (1994-03-01), Johnson
patent: 5373469 (1994-12-01), Akioka et al.
patent: 5384504 (1995-01-01), Dickinson et al.

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