Sense amplifier with dual parallel driver transistors in MOS ran

Details Sense amplifier with dual parallel driver transistors in MOS ran Sense amplifier with dual parallel driver transistors in MOS ran

1978-06-12

1981-08-25

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307DIG3, 365205, H03K 524, H03K 3353, G11C 706

Patent

active

042861780

ABSTRACT:
A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with a bistable sense amplifier circuit at the center of each column. Instead of a single pair of cross-coupled driver transistors forming the bistable circuit, dual parallel pairs are used. One pair used in the initial sensing has a long channel length so that the pair may be more readily matched, while the other pair used later in the cycle for driving the zero-going side of the column line to ground has a shorter channel to enhance speed.

REFERENCES:
patent: 3983412 (1976-09-01), Roberts et al.
patent: 4039861 (1977-08-01), Heller et al.
patent: 4045783 (1977-08-01), Harland
patent: 4050061 (1977-09-01), Kitagawa
patent: 4069475 (1978-01-01), Boettcher
patent: 4081701 (1978-03-01), White, Jr. et al.
patent: 4087704 (1978-05-01), Mehta et al.
patent: 4110841 (1978-08-01), Schroeder
patent: 4119870 (1978-10-01), Zibert
patent: 4150311 (1979-04-01), Matsuda et al.
Gionis, Ebel and Gegitz, -IEEE Journal of Solid-State Circuits; vol.-SC-10, No. 5, pp. 262-267; 10/1975.

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