Sense amplifier with bit-line derived clocking

Details Sense amplifier with bit-line derived clocking Sense amplifier with bit-line derived clocking

1987-08-27

1989-03-07

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, 307497, 365203, H03K 3356

Patent

active

048109100

ABSTRACT:
A sense amplifier device, as of CMOS technology includes a first (AN) and second (AP) amplifier responsive to the voltages (VB0, VB1) of two bit lines (B0, B1) to be amplified. When it is activated, the first amplifier (AN) connects the bit line having the lowest potential to ground potential. When the voltage of one of the bit lines is lower than a threshold voltage (VT), the second amplifier is triggered and connects the bit line having the highest potential to supply voltage.

REFERENCES:
patent: 4169233 (1979-09-01), Haraszti
patent: 4561702 (1985-12-01), McAdams
patent: 4606012 (1986-08-01), Koshizuka
patent: 4723228 (1988-02-01), Shah et al.

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