Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-07-27
2003-02-11
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06518827
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to semiconductor integrated circuits, and more particularly to a method and system for adjusting the threshold of devices. Specifically, to use control of the back-bias voltage in semiconductor devices, especially in DRAM sense amplifier circuits, to maintain an aimed-for value of the threshold voltage.
BACKGROUND OF THE INVENTION
Today's integrated circuits include a vast number of transistor devices formed in a semiconductor substrate, or body. In many integrated circuits, such as semiconductor memories or typical microprocessors, the devices formed in the semiconductor substrate are metal oxide semiconductor (“MOS”) devices. MOS devices come in two varieties, NMOS and PMOS devices. In most modern integrated circuits one finds both of these devices, and the name CMOS is used to describe such circuits. MOS de vices usually have three active terminals; these are the source, the drain, and the gate, the gate being the terminal where an input is typically applied. There is a voltage, called the threshold voltage, or just threshold V
th
, between the source and the gate that is important in device operation. Ideally, if the source to gate voltage exceeds the threshold value, the device conducts, or it is in the so called “on” state. Otherwise the device is in the “off” state and does not conduct. In an actual device, however, the transition between the on and off state is not quite as abrupt. Below the threshold the there is still a current flow between the source and the drain. This current, which flows when gate to source voltage is below the threshold voltage, is known as the leakage current.
The integrated circuits and the devices themselves are in a semiconductor substrate, or body. Consequently the whole device can be biased to certain voltage, or potential in relation to the substrate, or body. This bias is a fourth terminal to the device, and the body to source-terminal voltage is called the well-bias, or back-bias. In the following back-bias, well-bias, body-bias terms will be interchangeably used, since all have the same meaning. In modern CMOS circuits the devices are inside so called wells, not in direct electrical contact with the bulk of the substrate, hence the well-bias name. The back-bias also influences device behavior. An important effect of the back-bias is its influence on the device threshold. The further the back-bias goes in the, or toward, the reverse direction, the larger the threshold becomes. Traditionally, only reverse bias between the well and the source was used, but there is no reason in modern low voltage circuits not to consider a forward biasing back-bias in order to lower the threshold. In general, it is known in the art that the back-bias is a tool with which device thresholds in integrated circuits can be regulated.
As power supplies are reduced below 1-Volt, the question of thresholds is becoming ever more problematic. Setting thresholds at a too low value enhances leakage currents, leading to a variety of detrimental effects. On the other hand, too high a threshold leads to poor device performance. Compounding the difficulties are the unavoidable process and temperature variations, all influencing thresholds. The fabrication process that is used to create the integrated circuits on chips is marvelously precise. In spite of this, since there are many millions of devices on a typical chip, it is impossible to maintain completely uniform device behavior across a given chip, or even more so, between different chips. The power supply voltages being so low, a few hundredths of a volt difference in the thresholds due to process variations, something that in earlier times would not have even been noticed, can cause a major disruption in operation. Also, thresholds are sensitive to temperature. In general thresholds increase with decreasing temperature. Again, the threshold differences caused by temperature changes were manageable in earlier days, but are becoming a source of serious concern in modern circuits.
Some of the most vulnerable circuits to unwanted threshold variations are the DRAM sense amplifiers. The operation of these amplifiers involves a precharging step to a so called “bit-line equalization”, V
bleq
, voltage. This V
bleq
is roughly half of the power supply voltage. This means that the DRAM sense amplifiers are practically as sensitive to threshold variations as if the power supply voltage, already at dangerously low level, were further shrunk by a factor of two.
SUMMARY OF THE INVENTION
This invention deals with solving the issue of threshold variation in modern integrated circuits, and in particular to deal with the problem of DRAM sense amplifiers. Optimizing the V
th
of DRAM sense amplifier devices over process and temperature becomes very difficult. If thresholds, which during the fabrication process are adjusted by ion implants, are set for high-performance with low V
th
at low temperature, excessive leakage may occur at high temperature. This invention shows a system, and method thereof, for modulating the back-bias of the devices in order to meet a constant target, or aimed-for V
th
, independently of process and/or temperature variation, and for being able to further fine tune the threshold as the need arises.
Numerous innovations for using back-bias control on MOS devices are available in the prior art that now will be described. Even though these innovations may be suitable for the specific individual purposes which they address, they differ from the present invention.
For example, U.S. Pat. No. 6,048,746 to Burr, incorporated by reference herein, teaches the control of leakage current, but does not teach the present invention.
In a further example, U.S. Pat. No. 6,115,295 to V. Surlekar et al, incorporated by reference herein, teaches the use of back bias to initialize DRAMs, but does not teach the present invention.
In as yet another example. U.S. Pat. No. 6,163,044 to Manning et al, incorporated by reference herein, teaches power reduction through back-biasing with a “pump” circuit, but does not teach the present invention.
The use of back-bias control on MOS devices was also discussed in the recent technical literature. For instance, in “A well-Synchronized Sensing/Equalizing Method for Sub-1.0V Operating Advanced DRAMs” Ooishi et al. IEEE JSSC Vol 29, No. 4 April 1994, the concept of back bias control of DRAM sense amplifiers is discussed. However, there is no method to regulate the sense amplifier V
t
to a predetermined target value. Also in “Low Voltage Circuit Design Techniques for Battery Operated and/or Giga-Scale DRAMs” Yamagata et al., IEEE . . . JSCC Vol 30, no. 11, November 1995, control of a sense amplifier's back-bias is discussed. However, no circuit for controlling the sense amplifier V
t
, independently of process and temperature is shown.
This invention shows a method and circuits to achieve the goal for modulating the back-bias of the devices to meet a constant target, or aimed-for V
th
, independently of process and temperature variation, and for being able to further fine tune the threshold as the need arises.
In the present invention the method comprises a step of generating an indicating voltage. This indicating voltage contains information on the momentary V
t
value of devices, and in particular of the devices in DRAM sense amplifiers. The indicating voltage generating circuit has a plurality M, where M is in the order of 10, of MOS devices. These MOS devices in the indicating voltage generating circuit are processed to be identical to the DRAM sense amplifier devices. For the sake of specificity we discuss NMOS devices with the understanding that the invention covers the exact same case for PMOS devices with the semiconductor types of N and P interchanged. The M NMOS devices are connected in parallel to form a V
t
, indicator. The gates and drains of these indicator NMOSs are connected to a first voltage value. The first voltage can be any value that can easily and reproducibly generated. In one embodiment, this
Dennard Robert H.
Fifield John A.
Houghton Russell J.
Kirihara Toshiaki
Luk Wing
International Business Machines - Corporation
Nu Ton My-Trang
Sai-Halasz George
Underweiser Marian
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