Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-06-21
2002-10-01
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185240
Reexamination Certificate
active
06459620
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to sense amplifier circuits used to detect the states of non-volatile memory cells in a non-volatile memory array.
BACKGROUND OF THE INVENTION
Non-volatile memory (NVM) systems typically sense the content of a non-volatile memory cell by comparing the current through the cell (or the voltage derived from the current through the cell) to a reference current (or voltage). When the sensed current (or voltage) is larger than the reference current (or voltage), the cell is considered to be erased. If the sensed current (or voltage) is smaller than the reference current (or voltage), the cell is considered to be programmed.
The reference current (or voltage) is typically generated by applying read voltages to a reference non-volatile memory cell. The reference cell is programmed to have a desired reference threshold voltage during the production of the non-volatile memory system. As a result, the reference cell will provide a reference voltage representative of the reference threshold voltage. The most common method for controlling the programming of the threshold voltage of the reference cell is to read the current through the reference cell as the reference cell is being programmed.
FIG. 1
is a circuit diagram of a portion of a conventional non-volatile memory system
100
. NVM system
100
includes a reference voltage generation circuit
101
, non-volatile memory array sections
110
-
111
and comparators
130
-
131
. NVM array section
110
includes a plurality of NVM cells, including NVM cell
120
, and access multiplexers
107
-
108
. Similarly, NVM array section
111
includes a plurality of NVM cells, including NVM cell
121
, and access multiplexers
105
-
106
.
A read operation is performed as follows in NVM system
100
. Within NVM array section
110
, a first non-volatile memory cell
120
is selected to have a read word line voltage V
RWL
applied to its gate, a read bit line voltage V
RBL
applied to its source through multiplexer
107
, and its drain coupled to the signal input terminal (SIG) of comparator
130
through multiplexer
108
. The voltage applied to the SIG input terminal of comparator
130
is labeled as comparator input signal CI[
0
].
Similarly, within NVM array section
111
, a second non-volatile memory cell
121
is selected to have the read word line voltage V
RWL
applied to its gate, the read bit line voltage V
RBL
applied to its source through multiplexer
105
, and its drain coupled to the signal input terminal (SIG) of comparator
131
through multiplexer
106
. The voltage applied to the SIG input terminal of comparator
131
is labeled as comparator input signal CI[
1
].
Reference voltage generation circuit
101
includes a reference non-volatile memory cell
102
and access multiplexers
103
-
104
. Multiplexers
103
-
104
are designed to have the same electrical characteristics as corresponding multiplexers
105
-
106
and
107
-
108
in NVM array sections
110
and
111
. During a read operation, the read bit line voltage V
RBL
is applied to the source of NVM reference cell
102
through multiplexer
103
, and the read word line voltage V
RWL
is applied to the gate of NVM reference cell
102
. In response, a current (which is dependent on the previously programmed threshold voltage of reference cell
102
) flows through reference cell
102
. This current is routed through multiplexer
104
, and results in a reference voltage V
TREF
, which is applied to the reference input terminals (REF) of comparators
130
and
131
.
Comparators
130
and
131
experience random internal voltage offsets for various reasons, including device geometry mismatches and process fluctuations. Consequently, comparators
130
and
131
can be represented as ideal comparators
140
and
141
, respectively, having internal voltage offsets
150
and
151
, respectively. Internal voltage offset
150
has a value of V
OFF[0]
, and internal voltage offset
151
has a value of V
OFF[1]
. Because these internal voltage offsets
150
-
151
are random, it is likely that V
OFF[0]
is not equal to V
OFF[1]
.
In view of voltage offsets
150
and
151
, the voltages applied to the REF input terminals of ideal comparators
140
and
141
are equal to (V
TREF
+V
OFF[0]
) and (V
TREF
+V
OFF[1]
, respectively. Because ideal comparators
140
-
141
operate in response to different reference voltages, these ideal comparators
140
-
141
are subject to inaccuracies. For example, a CI[
0
] signal having a first voltage may cause comparator
130
to provide a logic high BIT[
0
] output signal, while a CI[
1
] signal having the same first voltage may cause comparator
131
to provide a logic low BIT[
1
] signal.
It would therefore be desirable to have a nonvolatile memory system that overcomes the above-described deficiencies of NVM system
100
.
SUMMARY
Accordingly, the present invention provides a non-volatile memory system that includes a dedicated NVM reference circuit coupled to each comparator. Each NVM reference circuit includes a NVM reference cell, which is initially programmed to have a threshold voltage that compensates for the internal voltage offset of the corresponding comparator. Compensating the NVM reference circuits in this manner enables all of the comparators to provide consistent results during a read operation.
In one embodiment, each of the NVM reference cells is programmed in the following manner. A first programming pulse is applied to the NVM reference cell. This first programming pulse has a relatively low programming voltage and a relatively short duration, such that the NVM reference cell is not fully programmed. The NVM reference cell is then subjected to a read verify condition, whereby a voltage representative of the programmed threshold voltage of the NVM reference cell is applied to the reference input terminal of the corresponding comparator. During the read verify operation, a predetermined reference voltage V
REF
is applied to the signal input terminal of the corresponding comparator. The predetermined reference voltage V
REF
is a voltage selected to differentiate between a logic high read output voltage and a logic low read output voltage.
If the comparator indicates that the voltage applied to the reference input terminal is less than the predetermined reference voltage V
REF
applied to the signal input terminal, then another programming pulse, having a slightly higher programming voltage, is applied to the NVM reference cell, and another read verify operation is performed.
This process continues until the comparator indicates that the voltage applied to the reference input terminal is greater than the predetermined reference voltage V
REF
during the read verify operation. At this time, the programming operation is stopped.
In this manner, the threshold voltage of the NVM reference cell is programmed such that when the NVM reference cell is subjected to read conditions, the voltage applied to the reference input terminal of the comparator will be equal to the predetermined reference voltage V
REF
, minus the offset voltage of the comparator. By programming the NVM reference cells in this manner, each of the NVM reference cells is properly referenced to the same predetermined reference voltage during subsequent read operation.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5157626 (1992-10-01), Watanabe
patent: 5694363 (1997-12-01), Calligaro et al.
patent: 5812456 (1998-09-01), Hull et al.
patent: 6128226 (2000-10-01), Eitan et al.
patent: 6292397 (2001-09-01), Kim
Bever Hoffman & Harms LLP
Hoffman E. Eric
Mai Son
Tower Semiconductor Ltd.
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