Sense amplifier of semiconductor integrated circuit

Details Sense amplifier of semiconductor integrated circuit Sense amplifier of semiconductor integrated circuit

2001-09-18

2002-11-05

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S052000, C365S207000

Reexamination Certificate

active

06476646

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly, to sense amplifiers and differential amplifiers.
2. Description of the Related Art
There are two types of sense amplifiers commonly used for amplifying signals in semiconductor integrated circuits, current sense amplifiers and voltage sense-amplifiers. Current sense amplifiers are widely used since they can operate faster than voltage sense amplifiers.
FIG. 1
shows a conventional sense amplifier circuit that includes a current sense amplifier
10
, a full differential amplifier
12
, and a latch
14
. When an enable signal EN is at a high level, NMOS transistors MN
11
, MN
5
, and MN
8
are on and provide current paths to enable operation of the current amplifier
10
, the full differential amplifier
12
, and the latch
14
, respectively. During a sensing time when the enable signal EN is at a high level, the voltage swings of the output signals SAOUT and SAOUTB of the current sense amplifier
10
are small. Accordingly, the amplification speed of the current sense amplifier
10
cannot directly convert the output signals SAOUT and SAOUTB to a CMOS voltage level. To increase the amplification speed, the full differential amplifier
12
further amplifies the output signal of the current sense amplifier
10
and outputs the amplified signals OUT and OUTB to the latch
14
. The latch
14
latches the output signals OUT and OUTB from the full differential amplifier
12
and provides latched output signals DOUT and DOUTB.
In differential amplifier
12
, a first NMOS transistor MN
1
, a second NMOS transistor MN
2
, a first PMOS transistor MP
1
, and a second PMOS transistor MP
2
operate as a first differential amplifying unit that generates the output signal OUT. When the voltage of an input signal SAOUT input through node
16
functioning as an input port becomes higher than the voltage of a complementary input signal SAOUTB input through node
18
functioning as a complementary input port, the voltage of the output signal OUT at an output port
24
increases. A third NMOS transistor MN
3
, a fourth NMOS transistor MN
4
, a third PMOS transistor MP
3
, and a fourth PMOS transistor MP
4
operate as a second differential amplifying unit that generates the complementary output signal OUTB. Accordingly, the voltage of the complementary output signal OUTB at a complementary output port
26
decreases when the voltage of the input signal SAOUT becomes higher than that of the complementary input signal SAOUTB.
When the voltage of the input signal SAOUT becomes lower than the voltage of the complementary input signal SAOUTB, the first differential amplifying unit decreases the voltage of the output signal OUT, and the second differential amplifying unit increases the voltage of the complementary output signal OUTB. The voltage difference between the output signal OUT and the complementary output signal OUTB is proportionate to the voltage difference between the input signal IN and the complementary input signal INB.
The output signal OUT and the complementary output signal OUTB are the input signals of the latch
14
. The latch
14
includes a sixth NMOS transistor MN
6
, a seventh NMOS transistor MN
7
, an eighth NMOS transistor MN
8
, a fifth PMOS transistor MP
5
, and a sixth PMOS transistor MP
6
. The latch
14
performs an effective latch operation when the voltage levels of the output signal OUT and the complementary output signal OUTB from the full differential amplifier
12
near the turn-on voltage of the NMOS transistors MN
6
and MN
7
, respectively. If either the output signal OUT or the complementary output signal OUTB is higher than the turn-on voltage of the corresponding NMOS transistor MN
6
or MN
7
, the latch
14
performs the latch operation when the other signal OUTB or OUT is lower than the turn-off voltage of the corresponding NMOS transistor MN
7
or MN
6
. In
FIG. 1
, the latch circuit
14
outputs the output signal DOUT and the complementary output signal DOUTB.
In general, transistors in the sense amplifier of
FIG. 1
are sized so that when a supply voltage VDD is low, the mean value of the output signal OUT and the complementary output signal OUTB is around the turn-on voltage of the NMOS transistors MN
6
and MN
7
. However, the channel length modulation effect of the PMOS transistors (e.g., transistors MP
1
, MP
2
, MP
3
, and MP
4
) becomes larger than the channel length modulation effect of the NMOS transistors (e.g., MN
1
, MN
2
, MN
3
, and MN
4
) as the supply voltage VDD increases. Accordingly, when the supply voltage VDD increases, the mean voltage of the output signal OUT and the complementary output signal OUTB increases. Accordingly, the NMOS transistors MN
6
and MN
7
in the latch
14
do not operate effectively. More specifically, the output signal OUT, which is applied to the gate of the sixth NMOS transistor MN
6
, and the complementary output signal OUTB, which is applied to the gate of the seventh NMOS transistor MN
7
, strongly turn on transistors MN
6
and MN
7
. This can cause errors in the latch operation. Accordingly, the latch circuit
14
can malfunction when the semiconductor integrated circuit is tested in a high voltage test enable (HITE) mode, where the supply voltage is a high voltage. Therefore, normal testing of the semiconductor integrated circuit in the HITE mode is not possible.
To solve the above problem, the design of the full differential amplifier
12
can make the second PMOS transistor MP
2
and the third PMOS transistor MP
3
smaller. In this case, the gain of the full differential amplifier is reduced.
The current sense amplifier
10
shown in
FIG. 1
is widely used since the current sense amplifier
10
operates faster than a voltage sense amplifier. However, the operation of the current sense amplifier
10
becomes unstable since a positive feedback circuit is used to effectively receive a current input signal. For the current sense amplifier
10
, reference numerals Il and I
2
denote current signals input through the input ports
15
and
17
, respectively. Signals SAOUT and SAOUTB are output through node
16
functioning as an output port and node
18
functioning as a complementary output port, respectively.
To explain the operation of the current sense amplifier
10
, the transconductance of the ninth NMOS transistor MN
9
and the tenth NMOS transistor MN
10
is referred to herein as gmn. The transconductance of the seventh PMOS transistor MP
7
and the eighth PMOS transistor MP
8
is referred to as gmp. &Dgr;I is the difference between the input current I
1
and the complementary input current I
2
(&Dgr;I=I
1
−I
2
). The voltage difference between the output voltage SAOUT and the complementary output voltage SAOUTB is about equal to &Dgr;I/gmn. The difference between the current value amplified by the seventh PMOS transistor MP
7
and the current value amplified by the eighth PMOS transistor MP
8
is &Dgr;I×gmp/gmn. Since this value must be equal to &Dgr;I, which is the difference between the input current signals I
1
and I
2
, the transconductance gmp of the PMOS transistors MP
7
and MP
8
must be equal to the transconductance gmn of the NMOS transistors MN
9
and MN
10
.
When the sizes of the seventh PMOS transistor MP
7
and the eighth PMOS transistor MP
8
are increased to increase the gains of the seventh PMOS transistor MP
7
and the eighth PMOS transistor MP
8
, transconductance gmp becomes larger than transconductance gmn. Accordingly, the seventh PMOS transistor MP
7
and the eighth PMOS transistor MP
8
amplify the input current signals with a current difference larger than &Dgr;I, which is the difference between the input current signals. Therefore, the values associated with the input current signals I
1
and I
2
can be exchanged, and the current sense amplifier
10
goes to an unstable state. The transconductance gmp must be less than or equal to transconductance gmn for stability. However, as transconductance gmp becomes sm

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