Sense amplifier having capacitively coupled input for offset com

Static information storage and retrieval – Floating gate – Particular biasing

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3651852, 3651853, 36518513, 36518907, 3652335, G11C 1606

Patent

active

057294925

ABSTRACT:
A sense amplifier circuit for a semiconductor memory device comprises a first current/voltage converter for convening a current of a memory cell to be read into a voltage signal, a second current/voltage converter for converting a reference current into a reference voltage signal, and a voltage comparator for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises a capacitive decoupler for decoupling the voltage signal from the comparator, and circuitry for providing the capacitive decoupler with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.

REFERENCES:
patent: 4264872 (1981-04-01), Suzuki
patent: 5289419 (1994-02-01), Hashizumi et al.
patent: 5305273 (1994-04-01), Jinbo
Terada, Y. et al., "120-ns 128K x 8-bit/64K x 16-bit CMOS EEPROM's," IEEE Journal of Solid-State Circuits 24:1244-1249, Oct., 1989.
Masuoka, F. et al., "A 256-kbit Flash E.sup.2 PROM Using Triple-Polysilicon Technology," IEEE Journal of Solid-State Circuits 22:548-552, Aug., 1987.

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