Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-01-23
1997-10-07
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular biasing
36518521, 365205, 365208, G11C 702
Patent
active
056755350
ABSTRACT:
In a sense amplifier for use in a semiconductor memory having a plurality of memory cells, comprising first and differential amplifiers receiving a potential signal read out from a selected memory cell and a reference potential, and having an output for respectively outputting first and second outputs differentially amplified in a phase opposite to each other, a CMOS inverter circuit is composed of a PMOS transistor and a NMOS transistor having their gate connected in common to receive the output of second differential amplifier. The CMOS inverter circuit has a threshold level corresponding to an intermediate level between a high logic level and a low logic level of binary information. An amplifier circuit is composed of a PMOS transistor having the same characteristics and the same size as those of the PMOS transistor of the CMOS inverter circuit and on-off controlled by an output signal of the CMOS inverter circuit, and a NMOS transistor having the same characteristics and the same size as those of the NMOS transistor of the CMOS inverter circuit and on-off controlled by an output of the first differential amplifier. A drain of the PMOS transistor and a drain of the NMOS transistor of the amplifier circuit are connected to each other so as to constitute a signal output node.
REFERENCES:
patent: 5197028 (1993-03-01), Nakai
D. Hoff et al., "A 23-ns 256K EPROM with Double-Layer Metal and Address Transition Detection", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1250-1258.
NEC Corporation
Popek Joseph A.
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