Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-11-20
2004-06-08
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185210, C365S185250, C365S185010
Reexamination Certificate
active
06747892
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to non-volatile integrated memory devices and more particularly to an improved sense amplifier and method of operating the same to quickly read data stored in a multi-state memory cell with a high degree of accuracy.
BACKGROUND OF THE INVENTION
Non-volatile memories, such as electronically erasable programable read-only memories (EEPROM) or flash memories, are widely used in portable devices including devices lacking a mass data storage devices and a fixed source of power, such as cellular phones, handheld personal computers (PCs), portable music players and digital cameras.
Non-volatile memories are typically semiconductor devices having a number of memory cells each with a field effect transistor having a control-gate and an isolated or floating-gate that is electrically isolated from a source and a drain of the FET. Non-volatile memories program or store information by injecting charge on the floating gate to change a threshold voltage of the FET. The injected charge changes the threshold voltage of the FET from an intrinsic threshold voltage by an amount proportional to the charge. The new threshold voltage of the FET in the memory cell represents one or more bits of programmed data or information. For example, in a simple memory cell storing a single bit of data, the FET threshold voltage is either raised to a value near a high end of the threshold voltage range or maintained at a value near a low end. These two programmed threshold voltages represent a logical one or a logical zero. These voltages program the memory cell to turn on or off, respectively, when read conditions are established, thereby enabling a read operation to determine if data stored in the memory cell is a logical one or a logical zero.
To read the bit stored in a simple memory cell, an intermediate threshold voltage is applied to the FET and a resulting current compared with a reference current. A memory cell programmed to a high threshold voltage, a logical one, will conduct less current than the reference current, and a memory cell programmed to a low threshold voltage, a logical zero, will conduct more current than the reference current. The current comparison is accomplished with a circuit known as a sense amplifier or, more commonly, a sense amp. For a simple memory cell, the output of the sense amplifier is a one bit digital signal representing the logical state of the data stored in the memory cell.
More sophisticated non-volatile memories have multilevel or multi-state memory cells enabling the storage of more than one bit per memory cell. Storing more than one bit per memory cell requires that the threshold voltage space of the memory cell be divided or partitioned into multiple regions or memory states, each associated with one of several threshold voltages representing one of several possible bits or data states. For example, a multi-state memory cell capable of storing two bits of data requires a threshold space having four memory states, and a multi-state memory cell storing three bits of data requires partitioning the threshold space into eight memory states. Exemplary flash memories having such multi-state memory cells are described in U.S. Pat. Nos. 5,043,940 and 5,434,825, which patents are incorporated herein by reference.
To exploit the concept of non-volatile memories having multi-state memory cells fully, the memory states should be packed as closely together as possible, with minimal threshold voltage separation for margin/discrimination overhead. Thus, reading a multi-state memory cell requires that the sense amplifier precisely resolve the programmed threshold voltage with margins much smaller than the separation between available memory states. For example, given a multi-state memory cell having FETs with a two-volt threshold voltage space and four bits per memory cell (sixteen memory states per memory cell), each memory state is 125 mV wide, which requires the sense amplifier to resolve threshold voltages to within a few millivolts. Typically, the sense amplifier must be able to resolve thresholds to within about 10 mV or less.
In addition to resolving small voltage differences, performance requirements dictate that the sense amplifier be able to determine the programed threshold voltage within a very short time. This can be very critical in non-volatile memories using a closed loop write, where the programming operation is followed by a verify operation, in which the sense amplifier checks whether the threshold voltage of the memory cell being programmed has reached the desired value. These performance and resolution requirements are difficult to satisfy simultaneously. Often, performance must be sacrificed to improve resolution and vice versa.
FIG. 1
shows a prior art sensing circuit, commonly known as a current sensing circuit. A current mirroring circuit
10
and multiple sense amplifiers
15
, generally one sense amplifier for each memory state, compare the current from memory cell
20
with multiple reference currents provided simultaneously by multiple reference current circuits
25
. A predetermined fixed voltage, higher than a maximum programmed threshold voltage, is applied to the control gate of the memory cell being read. The resultant memory cell current is mirrored using a P-channel FET to multiple P-channel FETs as shown in FIG.
1
. These multiple mirrored currents are compared to multiple reference currents by the multiple sense amps. The different reference currents are equal to current produced by programmed threshold voltages that correspond to boundaries of threshold voltage partitions. The digital outputs of the sense amps indicate the memory cell state.
While an improvement over earlier designs, this approach is not wholly satisfactory for a number of reasons. As arrays grow in size and have increasing numbers of memory cells, it is not feasible to provide the necessary current, generally on the order of tens of micro amperes (&mgr;A), to mirror for the larger number of cells. Furthermore, it is difficult to read the cell state by distinguishing small current levels.
In a so-called voltage sensing approach, shown in
FIGS. 2 and 3
, a voltage (V
BL
) on a bit-line
28
of the memory cell
20
is pre-charged to a reference voltage (V
PRE
) using a pre-charge voltage V
PRE
. Optionally, bit-line
28
of the memory cell
20
is pre-charged through a cascode device
32
. A control gate voltage (V
CG
) exceeding the maximum possible threshold voltage (V
T
) cell is applied to the control gate
28
. V
CG
is chosen in relation to V
T
such that an erased memory cell will always conduct with that magnitude of V
CG
. After a period of time, &Dgr;t, V
BL
is compared with a trip or reference voltage (V
TRP
) using an inverter or comparator
30
. Referring to
FIG. 3
, it is seen that if V
BL
is larger than V
TRP
after &Dgr;t, the cell
20
conducts less than an effective comparison current (I
COMP
), and therefore V
T
is higher and the cell is programmed. It can be shown that a simplified approximate expression for the effective comparison current is:
I
COMP
=C
BL
(
V
PRE
−V
TRP
)/(
A
v
·&Dgr;t
)
where AV is the voltage gain of the cascode device, and C
BL
is the bit-line capacitance.
If the memory cell
20
is a multilevel or multi-state memory cell, the V
T
can be determined more precisely by applying a sequence of different V
CG
voltages and comparing the resultant V
BL
voltages. For example, in one version of this approach known as half-stepping, a V
CG
of about half of a maximum possible V
CG
is applied. If the resultant V
BL
is less than V
TRP
, in a second iteration (or pass), a V
CG
that is half of the V
CG
applied in the first pass, or one-quarter of the maximum possible V
CG
is applied. If the resultant V
BL
is greater than expected, in the second or subsequent pass, a V
CG
that is 1.5·V
CG
applied in the first pass, or 75% of the maximum possible V
CG
is applied. The process continues until the V
T
is determined with sufficient precision.
While an improveme
Parsons Hsue & de Runtz LLP
SanDisk Corporation
Yoha Connie C.
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