Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-02-12
2002-10-15
Smith, Matthew (Department: 2825)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S056000
Reexamination Certificate
active
06466059
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior European Patent Application No. 98-830064.6, filed Feb. 13, 1998, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory devices, and more specifically to a sense amplifier for low voltage non-volatile memory devices.
2. Description of Related Art
In the following description, conventional terms for MOS (Metal Oxide Semiconductor) transistor technology are used. For example, the term “gate” indicates the control electrode or control gate of a MOS transistor, the term “drain” indicates the load electrode, and the term “source” indicates the source electrode. Further, the term “non-volatile” memory indicates a memory that does not lose stored data when the power supply is shut off, such as a ROM (Read Only Memory), EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and EAROM (Electrically-Alterable Read Only Memory).
In a conventional EEPROM, data is stored substantially by a MOS transistor. The MOS transistor includes two gate electrodes: a control gate that is electrically connected to the circuit and receives the gate voltage, and a floating gate that is separated from the control gate by an SiO
2
oxide barrier. Depending on the logic state to be stored, a positive or negative charge is trapped on the floating gate by applying appropriate voltages to the transistor. In particular, the charge is transferred by tunnel effect from the substrate to the floating gate, through the potential barrier of the oxide layer, and trapped on the floating gate.
The trapped charge acts on the voltage-current relationship of the transistor so that a change of the threshold voltage of the transistor takes place in accordance with the type of charge trapped on the floating gate. As a consequence of the threshold change, the memory cell formed by the MOS transistor can assume three different states—written, erased or virgin—depending on if the charge on the floating gate is of one type or the other, or if a charge has ever been applied. The correlation between the logic state, the sign of the trapped charge, and the cell state (written or erased) is a matter of design choice and can change from one product to another according to the selected convention.
The logic state of a cell can be identified by sensing the current flowing though the cell under known bias conditions. In particular, if a negative charge is trapped on the floating gate, the transistor threshold is higher than with a virgin transistor, and therefore with the same gate-source voltage a smaller current will flow. On the other hand, if a positive charge is trapped on the floating gate, the threshold voltage is lower than with a virgin transistor, and thus the current is greater. Thus, the logic state can be detected by using a sense amplifier to compare the current of a cell to the current of a virgin cell under the same biasing conditions.
Conventional sense amplifiers are substantially based on a current mirror that is arranged between two circuit branches: one connected to a virgin cell and another connected to a memory cell.
FIG. 1
shows a conventional sense amplifier. As shown, the sense amplifier is a substantially symmetric circuit having a reference branch REF and a second branch pertaining to a cell array MAT. To the reference branch REF, there is connected a reference cell MREF that consists of a floating gate transistor. The reference cell MREF is a virgin cell. To the branch pertaining to the cell array MAT, there is connected a selected cell MMAT. The reference cell MREF and the selected cell MMAT are connected to the sense amplifier
1
through a reference bit line BLREF and an array bit line BLMAT, respectively.
The selected cell MMAT is one of the cells of a memory array, which is not shown in its entirety for simplicity. The cells of the memory array are connected to the bit line of the array BLMAT through their drains, and cells are selected through a suitable decoding circuit (not shown). A reference current IREF flows through the reference cell MREF and is mirrored by the amplifier circuit
1
into the branch of the cell array MAT. In the reference branch REF, the amplifier circuit
1
is represented by a first N-channel MOS transistor N
1
whose gate is connected to an inverter INV
1
, which is controlled by the signal on the bit line BLREF.
A determined voltage VBLREF is fixed on the bit line BLREF, with the determined voltage VBLREF being the voltage on the drain of the reference cell MREF. The determined voltage VBLREF has such a value that between source and drain a voltage VDSREF sufficient to keep the reference cell MREF conducting is present. The voltage VBLREF depends on the threshold voltage of the inverter INV
1
and the threshold voltage VTN
1
of the first NMOS transistor N
1
. Between a supply voltage VDD and the drain of the first NMOS transistor N
1
, there is connected a first P-type MOS transistor P
1
as a load. The transistor P
1
has its gate and drain connected together in diode configuration so as to mirror the reference current IREF into the branch pertaining to the cell array MAT through a corresponding second P-type transistor P
2
.
Thus, the first and second PMOS transistors P
1
and P
2
build a current mirror MR. The voltages VDREF and VDCELL, which are respectively available on the first NMOS transistor N
1
drain (node DREF) and on a second NMOS transistor N
2
drain (node DMAT), are then brought to an amplifying stage AMP. The remaining portion of the branch of the cell array MAT is similar to the reference branch REF, and will not be further described. The sense amplifier
1
substantially performs a comparison between the reference current IREF and the cell current IMAT and obtains two corresponding voltages VDREF and VDCELL that are sent to the amplifying stage.
For a correct operation of the reference branch REF of the sense amplifier, the supply voltage VDD must fulfill the following equation.
VDD>VBLREF+VDSN
1
+|IVTP
1
|+OVP
1
(1)
where VDSN
1
is the necessary drain-source voltage of transistor N
1
, which is saturated in order to supply the reference current IREF; VTP
1
is the threshold voltage of the first PMOS transistor P
1
; and OVP
1
is the overdrive voltage necessary to supply the reference current IREF. In this manner, as node DREF is connected to the positive terminal of the amplifying stage AMP, and consequently node DMAT is connected to the negative terminal, the voltage VDREF at node DREF is in the range given by the following equation.
VBLREF+VDSN
1
<VDREF<VDD−|VTP
1
|−OVP
1
(2)
Further, the voltage VDREF is allowed to vary through a sufficient range because it is compared to the voltage VDCELL at node DMAT. If the selected cell MMAT requires a current IMAT greater than the reference current IREF, the voltage VDCELL is less than the voltage VDREF. If these currents are reversed, so are the resulting voltages. From equations (1) and (2), it derives that the supply voltage VDD must be greater than 2 volts to allow both correct operation of the reference branch REF (or the cell array MAT branch) and a sufficient variation voltage VDREF (or VDCELL).
FIG. 2
shows a sense amplifier
2
that is substantially similar to the sense amplifier of
FIG. 1
, but with two identical sense branches. The final amplifying stage AMP compares the voltages at the nodes DREF and DMAT. However, the sense amplifier of
FIG. 2
has the same disadvantage of the sense amplifier of FIG.
1
. In particular, the supply voltage must be suitably high to allow correct operation. This disadvantage is particularly serious in modem memory circuits in which it is desired to reduce the supply voltage in order to reduce the power consumption of the circuit.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the presen
Demange Nicolas
Gaibotti Maurizio
Bongini Stephen
Dinh Paul
Fleit Kain Gibbons Gutman & Bongini P.L.
Jorgenson Lisa K.
Smith Matthew
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