Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2002-02-28
2003-05-20
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S051000
Reexamination Certificate
active
06566929
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, a sense amplifier drive circuit of a semiconductor memory device and a method for amplifying data.
2. Background of the Related Art
A basic DRAM (Dynamic Random Access Memory) cell structure includes a single transistor and a single capacitor connected to each other. In the DRAM cell, a word line is activated during reading, writing and refreshing operations, and a charge that is stored in the single capacitor of the DRAM cell is carried on a bit line and amplified by a sense amplifier. In this respect, the bit line is precharged before the word line is activated.
When the charge carried on the bit line is amplified by the sense amplifier, the sense amplifier is first overdriven with a pre-set overdrive voltage and is then driven by an internal power supply voltage, for a speedy and easy amplification of the charge.
FIG. 1
illustrates a schematic circuit diagram of a sense amplifier circuit of a related art, and includes a sense amplifier
10
that amplifies a data signal carried on a bit line BL and a bit line bar BLB. A sense amplifier drive unit
20
selectively applies an overdrive voltage or an internal power supply voltage to the sense amplifier
10
. A control signal generator
30
generates first and second PMOS control signals SAP
1
and SAP
2
, and an NMOS control signal SAN, to control the sense amplifier drive unit
20
.
The sense amplifier
10
is a related art latch-type sense amplifier including a first PMOS transistor PM
1
and a first NMOS transistor NM
1
, connected in series between a PMOS drive line CSP and an NMOS drive line CSN, with their respective gates being commonly connected to a bit line BL via a first node N
1
. A second PMOS transistor PM
2
and a second NMOS transistor NM
2
are connected in series between the PMOS drive line CSP and the NMOS drive line CSN, with their respective gates being commonly connected to the bit line bar BLB via a second node N
2
. Here, the commonly connected drains of the second PMOS transistor PM
2
and the second NMOS transistor NM
2
serve as the first node N
1
, while the commonly connected drains of the first PMOS transistor PM
1
and the first NMOS transistor NM
1
serve as the second node N
2
.
The sense amplifier drive unit
20
includes a third NMOS transistor NM
3
that receives the first control signal SAP
1
at its gate and selectively applies an overdrive voltage VDDCLP to the PMOS drive line CSP of the sense amplifier
10
. A fourth NMOS transistor NM
4
receives the second PMOS control signal SAP
2
at its gate and selectively applies an internal power supply voltage VDL to the PMOS drive line CSP of the sense amplifier
10
. In addition, a fifth NMOS transistor NM
5
receives the NMOS control signal SAN at its gate and selectively connecting the NMOS drive line CSN of sense amplifier
10
to a ground voltage VSS.
FIG. 2
illustrates a detailed schematic circuit diagram of the control signal generator
30
that generates the first and second PMOS control signals SAP
1
and SAP
2
, and the NMOS control signal SAN. As shown in
FIG. 2
, the control signal generator
30
includes first and second inverters INV
1
and INV
2
, each inverting a sense amplifier enable bar signal SAENB. A delay circuit DE
1
delays an output signal from the second inverter INV
2
for a predetermined time. A third inverter INV
3
inverts an output signal from the delay circuit DE
1
. A first NOR gate NOR
1
provides a NOR operation to an output signal from the third inverter INV
3
and the sense amplifier enable bar signal SAENB. A fourth inverter INV
4
inverts an output signal from the first inverter INV
1
, and outputs the Inverted output signal to a logic circuit
31
. A fifth inverter INV
5
inverts an output signal from the first NOR gate NOR
1
and outputs the inverted output signal to the logic circuit
31
.
The logic circuit
31
includes three control signal generator sections
31
a-c
, and a sixth inverter INV
6
that inverts the output signal from the fifth inverter INV
5
. The first control signal generator section
31
a
includes a second NOR gate NOR
2
that provides a not OR operation to the output signal from the sixth inverter INV
6
and an output signal from the fourth inverter INV
4
. Seventh and eighth inverters INV
7
and INV
8
sequentially invert an output signal from the second NOR gate NOR
2
as the first PMOS control signal SAP
1
.
The second control signal generator section
31
b
includes a ninth inverter INV
9
that inverts an output signal from the sixth inverter INV
6
, and a first NAND gate ND
1
that provides a not AND operation to the output signal from the fourth inverter INV
4
and an output signal of the ninth inverter INV
9
. Tenth and eleventh inverters INV
10
and INV
11
sequentially invert an output signal from the first NAND gate ND
1
as the NMOS control signal SAN. The third control signal generator section
31
c
includes twelfth to fifteenth inverters INV
12
-INV
15
that sequentially invert the output signal from the sixth inverter INV
6
as the second PMOS control signal SAP
2
.
FIG. 3
illustrates an operational timing diagram of the related art sense amplifier drive unit of FIG.
1
. When the sense amplifier enable bar signal SAENB is applied to the control signal generator
30
, the first and second PMOS control signals SAP
1
and SAP
2
and the NMOS control signal SAN are output to the sense amplifier drive unit
20
.
As shown in
FIG. 3
, the first and the second PMOS control signals SAP
1
and SAP
2
are sequentially enabled. That is, at the time when the first PMOS control signal SAP
1
is disabled after being enabled, the second PMOS control signal SAP
2
is enabled. Accordingly, the third and fourth NMOS transistors NM
3
and NM
4
of the sense amplifier drive unit
20
are sequentially turned on and the overdrive voltage VDDCLP and the internal power supply voltage VDL are sequentially applied to the PMOS drive line CSP of the sense amplifier
10
.
In other words, while the first PMOS control signal SAP
1
is enabled, the third NMOS transistor NM
3
is turned on, and the sense amplifier
10
is driven by the overdrive voltage VDDCLP, so that the data carried on the bit line BL and the bit line bar BLB is amplified to the level of the overdrive voltage VDDCLP.
Subsequently, the first PMOS control signal SAP
1
is disabled to turn off the third NMOS transistor NM
3
, and at this time, the second PMOS control signal SAP
2
is enabled to turn on the fourth NMOS transistor NM
4
. Then, the sense amplifier
10
is driven by the internal power supply voltage VDL, so that the data carried on the bit line BL and the bit line bar BLB is amplified to the level of the internal power supply voltage VDL.
The related sense amplifier drive circuit, however, has a problem that an unnecessary current consumption unavoidably occurs because the overdrive voltage is supplied to the sense amplifier
10
during a refreshing operation.
SUMMARY OF THE INVENTION
An object of the present invention is to substantially obviate one or more of the problems of the related art and provide at least the advantages set forth below.
Another object of the present invention is to reduce an unnecessary current consumption.
Another object of the present invention is to prevent an application of an overdrive voltage during a refresh operation.
The objects of the present invention can be achieved, in whole or in parts, by a sense amplifier drive circuit including a sense amplifier that amplifies data carried on a bit line and a bit line bar; a sense amplifier drive unit that selectively applies an overdrive voltage and an internal power supply voltage to the sense amplifier; and a control signal generator that combines a sense amplifier enable bar signal and a refresh enable signal, and generates control signals to control the sense amplifier drive unit.
The objects of the present invention can also be achieved, in whole or in parts, by a circuit including a control signal gener
Cunningham Terry D.
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Nguyen Long
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