Sense amplifier circuit for reducing transmission delay in data

Details Sense amplifier circuit for reducing transmission delay in data Sense amplifier circuit for reducing transmission delay in data

1992-05-26

1994-07-19

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307355, 307555, 307491, 365190, H03F 345, G11C 702, G11C 706, G01R 19155

Patent

active

053312333

ABSTRACT:
A plurality of differential amplifier circuits are supplied with respective potentials of a plurality of paired bit lines and subjects the potentials of the bit line pairs to the differential amplification. The plurality of differential amplifier circuits are connected to paired data lines. The paired data lines are connected at one end to a first clamping circuit for clamping the potential of the paired data lines. The first clamping circuit is connected to a common load circuit acting as a common load for the plurality of differential amplifier circuits. The paired data lines are connected at the other end to a second clamping circuit for reducing the amplitude of a voltage between the paired data lines.

REFERENCES:
patent: 4479202 (1984-10-01), Uchida
patent: 4606012 (1986-08-01), Koshizuka
patent: 4739198 (1988-04-01), Maruyama
patent: 4939693 (1990-07-01), Tran
patent: 4948993 (1990-08-01), Chin et al.
K. Ogiue et al., 13-ns, 500-mW, 64-kbit ECL RAM Using HI-BICMOS Technology, IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 681-685.
M. Takada et al., A 5-ns 1-Mb ECL BiCMOS SRAM, IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1057-1062.
R. A. Kertis et al., A 12ns 256K BiCMOS SRAM, 1988 IEEE International Solid-State Circuits Conference.

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