Sense amplifier circuit for a flash memory device

Details Sense amplifier circuit for a flash memory device Sense amplifier circuit for a flash memory device

2001-05-30

2002-12-03

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S203000

Reexamination Certificate

active

06490199

ABSTRACT:

BACKGROUND
1. Technical Field
The present invention relates generally to semiconductor memory devices and, in particular, to a sense amplifier circuit for a flash memory device, the sense amplifier for detecting states of a memory cell.
2. Background Description
Nonvolatile flash memory devices have been widely used. An electrically erasable and electrically programmable memory cell of a flash memory device is formed of a floating gate transistor. The floating gate transistor has N-type source and drain regions, a floating gate, and a control gate. The N-type source and drain regions are formed on a P-type semiconductor substrate (or bulk). The floating gate is formed on a thin insulation film (or tunnel oxide film) on a channel region between the source and drain regions, and has a thickness less than 100 Å. The control gate is used as a word line formed on the floating gate. The memory cell is programmed by hot electron injection, which is well known in the art. When the memory cell is programmed, it is in a non-conducting state. The programmed memory cell is erased by an F-N tunneling method, which is also well known in the art. When the memory cell is erased, it is in a conducting state.
A sense amplifier circuit is used to detect whether a memory cell is in a conducting or non-conducting stage.
FIG. 5
is a diagram illustrating a conventional sense amplifier. As shown, the conventional sense amplifier circuit is of a single-ended type. The sense amplifier circuit is electrically connected to a bit line BL through NMOS transistors
10
and
12
, which compose a decoding circuit that couples the bit line BL to a data line DL. An electrically erasable and programmable memory cell MC is connected to the bit line BL.
The sense amplifier circuit is constructed of three PMOS transistors
14
,
16
, and
18
, three NMOS transistors
20
,
22
, and
24
, and three inverters
26
,
28
, and
30
. Current paths of the PMOS transistors
14
and
16
are formed in series between a power supply voltage Vcc (utilized as a first supply voltage) and sense node SO. A control signal Vload is applied to a gate of the PMOS transistor
14
. A gate of the PMOS transistor
16
is connected to the sense node SO. The NMOS transistor
20
has a current path formed between the sense node SO and the data line DL. Current paths of the PMOS transistor
18
and NMOS transistor
22
are formed in series between the power supply voltage Vcc and the data line DL. A control signal Vpre is applied to a gate of the PMOS transistor
18
. Gates of the NMOS transistors
20
and
22
are controlled by an output voltage BIAS of the inverter
26
connected to the data line DL. A voltage of the sense node SO is generated as a sense data nSAOUT through the inverters
28
and
30
. The NMOS transistor
24
is connected between the data line DL and a ground voltage GND (utilized as a second supply voltage), and is switched by a control signal Vdis.
In the operation of the sense amplifier circuit, an address is changed so as to select a memory cell(s), and then row address decoding signals YA and YB are activated to the high level, thus turning on the NMOS transistors
10
and
12
that compose the decoding circuit. The bit line BL and the data line DL are electrically connected through the NMOS transistors
10
and
12
, when the NMOS transistors
10
and
12
are turned on.
FIG. 6
is a timing diagram illustrating an operation of the sense amplifier circuit of FIG.
5
. Referring to
FIG. 6
, before the bit line BL and the data line DL are electrically connected with each other, a voltage of the data line DL is discharged. Namely, the control signal Vdis for discharging the data line DL voltage is activated to high during a predetermined time. During an activation period of the Vdis, the data line DL voltage is initialized by the NMOS transistor
24
, e.g., to lower than 0.5 V.
After discharging, the control signal Vpre is activated from a high level to a low level, resulting in a current flowing from the power supply voltage Vcc to the data line DL through the PMOS transistor
18
and the NMOS transistor
22
. Then, the data line DL voltage increases. As shown in
FIG. 6
, the current flows to the data line DL through the PMOS transistor
18
and the NMOS transistor
22
and, simultaneously, a current flows to the data line DL through the PMOS transistors
14
,
16
, and the NMOS transistor
20
. This is because the control signal Vload is activated to the low level after the control signal Vpre is activated. As the data line DL voltage gradually increases to the high level, the output voltage BIAS from the inverter
26
starts to attenuate in proportion to the increase of the data line DL voltage. The current provided to the data line DL through NMOS transistors
20
and
22
is decreased by the attenuation of the output voltage BIAS from the inverter
26
. The data line DL voltage is charged to a predetermined voltage level, e.g., 0.8 V. The control signal Vpre applied to the gate of the PMOS transistor
18
is inactivated to the high level. The control signal Vload is activated to the low level after the control signal Vpre is activated during a predetermined time period. However, the control signal Vload can be designed to be activated to the low level at the same time the control signal Vpre is activated.
Subsequently, when a voltage of the word line WL increases, the voltage of the data line DL is increased or decreased based upon the state of the memory cell, that is, whether the memory cell is in a conducting or non-conducting state. A current that flows through a memory cell in the conducting state is typically designed to be larger than a current that flows through the transistors
14
and
20
. Under these conditions, if the memory cell is in the conducting state, then the voltage of the sense node SO is attenuated by the data line DL voltage to be lower than that of a pre-charged voltage. The attenuated voltage of the sense node SO is converted into a digital signal (or is detected) by the inverter
28
. In contrast, if the memory cell is in a non-conducting state, then the current does not flow through the memory cell. The current flows to the data line DL and the sense node SO through the load transistor
14
, and then the sense node SO voltage is increased. The increased sense node SO voltage is converted into a digital signal (or is detected) by the inverter
28
.
However, the conventional sense amplifier circuit has a problem as described below. In a latter part of the pre-charge period, the output voltage BIAS from the inverter
26
(i.e., a gate voltage of the NMOS transistor
22
) is attenuated by the increased voltage of the data line DL.
FIG. 7
is a graph illustrating pre-charge characteristics in accordance with the prior art. As shown, a difference between the source voltage (or data line voltage) of the NMOS transistor
22
and the gate voltage BIAS is reduced, whereby a current I
22
provided through the NMOS transistor
22
is sharply attenuated in the latter part of the pre-charge period. Therefore, it typically takes more time to pre-charge the data line DL (or bit line connected to the data line electrically) to a desired voltage.
SUMMARY OF THE INVENTION
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a sense amplifier circuit that reduces a pre-charging time of a data line (or bit line) in a semiconductor memory device.
According to an aspect of the invention, in a flash memory circuit having a plurality of electrically erasable or programmable memory cells and a decoding circuit for electrically connecting a bit line corresponding to a selected memory cell to a data line, a sense amplifier circuit is provided for detecting an on/off state of the selected memory cell by sensing a voltage fluctuation of the bit line. The sense amplifier includes a bias circuit for generating a constant bias voltage during a pre-charge period. A first pre-charge circuit provides a variable current to the data line. The variable

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