Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-01-15
2003-12-16
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S210130
Reexamination Certificate
active
06665213
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to sense amplification for memory devices, and particularly to circuitry for more efficiently performing sense amplification in nonvolatile memory devices.
2. Description of the Related Art
The first nonvolatile memories were electrically programmable read-only memories (EPROMs). In these memories, the memory cells include a floating-gate transistor that is programmable using the hot carrier effect. Programming of an EPROM memory cell includes applying a potential difference between the drain and the source of the floating gate transistor in the presence of a high potential difference (of about 20 volts, this value varying according to the desired programming speed) between the control gate and the source. The application of the first of these potential differences generates an electrical field that gives rise to a flow of electrons in the channel. These electrons collide with atoms of the channel, causing the appearance of new free electrons. These electrons have very high energy (hence the term “hot carriers”). The high difference in potential between the control gate and the source of the floating gate transistor gives rise to a strong electrical field between the floating gate and the substrate, is the effect of which is that certain of these electrons are injected into the floating gate, thus putting the memory cell in a state known as a “programmed” state.
The fact that the programming of a memory cell requires the application of voltages both to the control gate and to the drain of the floating-gate transistor eliminates the need for the use of a selection transistor to program one particular memory cell without programming the others. This results in a relatively small silicon area and the effectuation of large scale integration. By contrast, the erasure of all the memory cells of the memory is done substantially simultaneously by exposing the memory cells to ultraviolet radiation.
In addressing the need to individually erase EPROM memory cells, electrically erasable programmable read only memories (EEPROMs) were created. These memories are electrically programmable and erasable by tunnel effect (i.e., the Fowler Nordheim effect). The memory cells have a. floating-gate transistor whose drain is connected to the bit line by a selection transistor. The gate of the selection transistor is connected to the word line. The gate of the floating-gate transistor is controlled by a bias transistor. Generally, the source of the floating gate transistor is connected to a reference potential, such as ground. These floating-gate transistors have an oxide layer between the substrate and the floating gate that is very thin to enable the transfer of charges by tunnel effect. The advantage of EEPROMs as compared with EPROMs lies in the fact that each memory cell is programmable and erasable independently of the other EEPROM cells. The tradeoff here is that a larger surface area of silicon is required and therefore a smaller scale of integration is achieved.
A third type of memory has more recently gained popularity. This type of memory, flash EPROMs, combines the relatively high integration of EPROMs with the ease of programming and erasure of EEPROMs. Flash memory cells can be individually programmed utilizing the hot carrier effect in the same way as EPROM cells are programmed. Flash memory cells are also electrically erasable by the tunnel effect. The memory cells of a flash EPROM memory includes a floating-gate transistor that has an oxide layer whose thickness is greater than the oxide layer thickness of an EEPROM floating gate transistor but smaller than the oxide layer thickness of an EPROM floating gate transistor. Consequently, the flash memory cell is capable of erasure by the tunnel effect. For erasure, a highly negative potential difference is created between the control gate and the source of the floating gate transistor, the drain being left in the high impedance state or connected to the ground potential so that a high electrical field is created which tends to remove the electrons from the floating gate.
Flash EPROM devices, hereinafter referred to as flash memory devices, typically include at least one array of flash memory cells organized into rows and columns of flash memory cells. The array is typically partitioned into blocks, each of which is further divided into sectors. A raw decoder and column decoder are used to select a single row and at least one column of memory cells based upon the value of an externally generated address applied to the flash memory device. Sense amplifiers are coupled to the column lines corresponding to the columns of memory cells to amplify the voltage levels on the addressed column lines corresponding to the data values stored in the addressed flash memory cells. The particular implementations of the array and the row and column decoders are known in the art and will not be described further for reasons of simplicity.
A conventional sense amplifier circuit includes a differential amplifier circuit that generally senses a voltage differential between the voltage appearing on a column line connected to a reference cell and the voltage appearing on a column line connected to an addressed memory cell, and drives a sense output signal (that is coupled to the data output pins of the flash memory device) based upon the sensed voltage differential. The conventional sense amplifier is sized and/or powered to provide a sense output signal with a relatively high slew rate so as to reduce the time needed for the sense amplifier to sense the voltage differential and suitably drive the sense output signal.
A problem exists in these conventional sense amplifiers for flash memory devices, however, in that the sense amplifier is activated during the precharge cycle (i.e., during the period of time the column lines are precharged) of a memory access operation in order to reach a stable operating state prior to the occurrence of the sense cycle (i.e., during the period of time that the addressed memory cells are coupled to the sense amplifiers). This extended period of sense amplifier activation, combined with the sense amplifiers drawing a relatively large amount of current, disadvantageously results in the conventional flash memory device dissipating a relatively high amount of power when in use. This problem is compounded by the fact that more sense amplifiers are now being used in state-of-the-art burst flash devices to allow higher bandwidth (data rate) and higher frequencies for high performance systems. Consequently, the current draw and/or power dissipation of sense amplifiers for flash memory devices is no longer a trivial consideration.
Based upon the foregoing, there is a need for a sense amplifier that more efficiently performs sense amplification in a flash memory device during memory access operations.
SUMMARY OF THE INVENTION
The present invention overcomes the shortcomings in prior systems and thereby satisfies a significant need for an improved sense amplifier for a nonvolatile memory device. In accordance with an exemplary embodiment of the present invention, the sense amplifier includes a pair of source-coupled input transistors. The control or gate terminal of a first of the input transistors is driven to a voltage level based upon a current level in an addressed memory cell during a memory access operation. The control terminal of a second of the input transistors is driven to a voltage level based upon a current level in a reference cell during the memory access operation. The sense amplifier further includes a pair of load elements, with each load element being coupled between the drain terminal of a distinct one of the input transistors and a first reference voltage source, such as a ground reference. A current source is coupled between the source terminals of the input transistors and a second reference voltage source, such as a power supply source, and configurable to draw any of at least two non-zero current levels through the current
Michael Oron
Sever Ilan
Jorgenson Lisa K.
Phan Trong
STMicroelectronics Inc.
Szuwalski Andre
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