Sense amplifier circuit

Details Sense amplifier circuit Sense amplifier circuit

2001-05-21

2002-10-22

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C365S207000

Reexamination Certificate

active

06469546

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sense amplifier circuit incorporated in a circuit having complementary data lines. More particularly, the present invention relates to a sense amplifier circuit incorporated in a dynamic random access memory (hereinafter referred to as a “DRAM”), etc., which requires a memory holding operation, which operates even with a low power supply voltage, which has a reduced power consumption, and which has a high data amplification speed.
2. Description of the Related Art
Recently, the increase in the application of semiconductor memory devices to portable equipments has prompted a reduction in the voltage of the semiconductor memory devices. Particularly, among other semiconductor memory devices, DRAMs, which require a memory holding operation, have a reduced voltage. The operating power supply voltage of some DRAMs is 2.5 V or less. For such DRAMs whose voltage has been reduced, the operation margin of a sense amplifier circuit has been an issue to be solved. The initial signal voltage AVsig from a memory cell of a sense amplifier circuit is represented by Expression 1 below.
&Dgr;
V
sig=(1/2
V
cc)/(1
+Cb/Cs
)  (Expression 1)
(Vcc: operating power supply voltage, Cb: bit line capacitance, Cs: memory cell capacitance)
As shown in Expression 1 above, a reduction in the operating power supply voltage Vcc reduces the initial signal voltage &Dgr;Vsig, thereby reducing the operation margin of the sense amplifier. In view of this, it has been proposed in the prior art to perform a sense amplification operation after the initial signal voltage &Dgr;Vsig is increased in the sense amplifier circuit (Heller, L. G., “Cross-Coupled Charge-Transfer Sense Amplifier,” ISSCC Digest of Technical Papers, pp20-21, Febuary, 1979 (conventional example 1)).
FIG. 1
is a circuit diagram illustrating a sense amplifier circuit of conventional example 1,
FIG. 2
is a block diagram of
FIG. 1
, and
FIG. 3
is a timing chart illustrating the operation of the sense amplifier circuit of the conventional example 1.
The sense amplifier circuit of the conventional example 1 uses n-channel MOS transistors. The sense amplifier circuit includes a pre-amplifier including transistors T
5
and T
6
, and an n-channel flip flop including transistors T
3
and T
4
. The sources of the transistors T
3
and T
5
are connected to each other, and the gates thereof are connected to a node D
2
in the sense amplifier. The sources of the transistors T
4
and T
6
are connected to each other, and the gates thereof are connected to a node D
1
in the sense amplifier. A sense amplifier driving line V
5
is connected to the drains of the transistors T
3
and T
4
.
A sense amplifier potential pull-up signal line V
2
is connected to the gate of each of the transistors T
5
and T
6
via a capacitor C
1
. The node D
2
is provided between the transistor T
4
and the transistor T
6
, and the source of a transistor T
2
is connected to the node D
2
therebetween. The transistor T
2
is provided with a terminal
102
at its drain, and a sense amplifier driving potential (hereinafter referred to as “VI”) is applied to the terminal
102
. Similarly, the node D
1
is provided between the transistor T
3
and the transistor T
5
, and the source of a transistor T
1
is connected to the node D
1
therebetween. The transistor T
1
is provided with a terminal
102
at its drain, and VI is applied to the terminal
102
.
A digit line D
6
is connected to the drain of the transistor T
6
. The digit line D
6
is connected to the sources of transistors T
8
and T
10
. The drain of the transistor T
8
is connected to a terminal
103
. A digit line high potential (hereinafter referred to as “VH”) is applied to the terminal
103
. A digit line pull-up signal line V
3
is connected to the gate of the transistor T
8
, and a digit line pull-down signal line V
4
is connected to the gate of the transistor T
10
.
A memory cell including one transistor
100
and one capacitor
101
is connected to the digit line D
6
, and a word line WL is connected to the memory cell. The sense amplifier circuit is incorporated in a DRAM, and has a left-right symmetric configuration. A digit line D
5
is connected to the drain of the transistor T
5
. The configurations of transistors T
7
and T
9
and the memory cell which are connected to the digit line D
5
are the same as those which are connected to the digit line D
6
, and thus will not be further described below.
As illustrated in
FIG. 2
which is a block diagram of the conventional example 1, an n-channel flip flop
110
, a precharge circuit
111
, and a digit line VH precharge circuit
112
for precharging the digit lines D
5
and D
6
to the potential of VH, are connected in parallel between complementary bit lines BLT
0
and BLN
0
. The transistor T
5
is provided along the bit line BLT
0
between the precharge circuit
111
and the digit line VH precharge circuit
112
, and the transistor T
6
is provided along the bit line BLN
0
therebetween. The gate of the transistor T
5
is connected to the complementary bit line BLN
0
, and the gate of the transistor T
6
is connected to the bit line BLT
0
.
Next, the operation of the conventional example 1 will be described. As illustrated in
FIG. 3
, at the beginning of the operation, the digit lines D
5
, D
6
are precharged from GND to VI-Vth (transistor threshold potential) via the transistors T
1
and T
5
, and T
2
and T
6
, respectively. As the potential of the word line WL transitions to a high level, a large potential difference occurs between the nodes D
1
and D
2
due to a charge transfer. VI-Vth is about VH/2. Thus, the capacitance of the digit lines D
5
and D
6
is greater than that of the nodes D
1
and D
2
.
Then, when the word line WL rises and if the digit line D
6
side is at a low level, the gate-source potential VGS of the transistor T
6
becomes greater than the threshold potential Vth of the transistor T
6
, thereby turning ON the transistor T
6
, whereby a charge moves from the node D
2
to the digit line D
6
. At this time, on the node D
2
side, due to the capacitance difference between the digit line D
6
and the node D
2
, a potential difference greater than that occurring on the digit line D
6
side occurs when the word line WL rises.
Then, when the potential of the sense amplifier pull-up signal line V
2
transitions to the high level, the potential difference between the nodes D
1
and D
2
has a magnitude which is at least Vth or more of the transistors T
5
and T
6
(n-channel transistors) due to the capacitor C
1
. Thereafter, the digit lines D
5
and D
6
are precharged to VH by the transistors T
7
and T
8
, respectively, and the potentials at the nodes D
1
and D
2
and the digit lines D
5
and D
6
are amplified to the high level or the low level by turning ON the transistors T
3
and T
4
while bringing the potential of the sense amplifier driving line V
5
to the low level so as to activate the n-channel flip flop. Then, at the end of the operation, the potential of the word line WL is brought to the low level and the potential of the sense amplifier driving line V
5
is brought to the high level so as to turn OFF the n-channel flip flop, and the potential of the digit line pull-down signal line V
4
is brought to the high level so as to reduce the potential of the digit lines D
5
and D
6
to GND.
As another method for sense-amplifying an initial voltage signal, for example, Tsukude, M., et al. “A 1/2 V to 3.3 V Wide-Voltage-Range DRAM with 0.8 V Array operation,” ISSCC Digest of Technical Papers, pp66-67, Febuary, 1997 (conventional example 2) has been proposed in the art.
FIG. 4
is a circuit diagram illustrating a sense amplifier circuit of conventional example 2,
FIG. 5
is a block diagram of
FIG. 4
, and
FIG. 6
is a timing diagram illustrating the operation of the sense amplifier circuit of the conventional example 2.
The sense amplifier circuit of the conventional example 2 has a CMOS configuration, and includes

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