Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1998-10-14
2001-07-24
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S056000, C327S066000
Reexamination Certificate
active
06265906
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to current-mirror-type sense-amplifier circuits that can be effectively applied in a multivalued-information memory for storing three or more values in each of its memory cells.
There has been proposed a multivalued-information memory capable of storing three or more values in each of its memory cells. This is realized in such a manner that plural threshold potential values are preset for each memory cell by changing an amount of impurities induced into channel areas of the memory cell for a mask ROM or by changing an amount of stored charge of floating gates for a flash E
2
PROM. The discrimination of these threshold potentials is conducted by comparing each potential at each bit line with plural reference values corresponding to the threshold potential values of the memory cell.
In case of storing, e.g., four-value information in each memory cell with bit-line potentials corresponding to respective threshold potential values expressed as VTH
1
, VTH
2
, VTH
3
and VTH
4
, the first reference potential value VREF
1
is set to a certain value between the values VTH
1
and VTH
2
, the second reference potential value VREF
2
is set to a certain value between the values VTH
2
and VTH
3
and the third reference potential value VREF
3
is set to a certain value between the values VTH
3
and VTH
4
. The above reference values are used by sub sense-amplifiers SL
1
, SL
2
and SL
3
as shown in
FIG. 1. A
bit-line potential VBIT is one of the values VTH
1
, VTH
2
, VTH
3
and VTH
4
and, therefore, output signals SAl, SA
2
and SA
3
corresponding to the bit-line potentials are obtained.
FIG. 2
shows a relationship between bit-line potentials and reference potentials. CE is a signal for activating a sense amplifier. Two-bit information (D
1
, D
2
in
FIG. 4
) according to the above-described output signals SA
1
, SA
2
and SA
3
can be readout by a circuit of FIG.
3
.
Japanese Laid-open Patent Publication No. 5-217385 discloses a sense amplifier circuit used for a mask ROM. In the disclosure, as shown in
FIG. 5
, the sense amplifier is applied for a mask ROM for storing four-valued information in each of memory cells, wherein four bit-line potentials VTH
1
, VTH
2
, VTH
3
and VTH
4
are used as reference potentials corresponding to respective thresholds of the memory cell. The amplifier circuit is provided with three sub sense-amplifiers SL
1
, SL
2
and SL
3
, each of which comprises a current mirror circuit. The first sub sense-amplifier SL
1
is given the first and second bit-line potentials VTH
1
and VTH
2
as reference potentials, the second sub sense-amplifier SL
2
is given the second and third bit-line potentials VTH
2
and VTH
3
as reference potentials and the third sub sense-amplifier SL
3
is given the third and fourth bit-line potentials VTH
3
and VTH
4
. This enables the amplifier circuit to use reference bit-lines having the same construction as that of the corresponding bit-lines of the memory cell, thus realizing stable reading of the potentials.
Referring now to
FIGS. 6 and 7
, a current-mirror-type sense-amplifier will be described as bellow:
As seen in
FIG. 6
, the first static inverter is composed of a n-type metal-oxide silicon field-effect transistor MOSFET QN
1
and a p-type MOSFET QP
1
and the second static inverter is composed of a n-type MOSFET QN
2
and a p-type MOSFET QP
2
: both the converters are in parallel to each other and connected each at one end to the ground potential (GND) through a n-type MOSFET QN
3
. The static converters are also connected each at the other end to the power-source potential (Vcc). With the signal CE for activating the sense-amplifier, the n-type MOSFET QN
3
conducts bringing the sense-amplifier into the state being ready to work. The p-type MOSFET QP
1
and QP
2
compose a load side of the current mirror. The n-type MOSFET QN
1
and QN
2
are supplied with input potentials to be compared with each other. Namely, a reference potential VREF is input to a gate of the n-type MOSFET QN
1
and a bit-line potential VBIT is fed to a gate of the n-type MOSFET QN
2
. A difference between those potentials is detected and output as an output signal VOUT.
In the first static inverter, the p-type MOSFET QP
1
operating in the saturated mode (region) possesses a load characteristic curve (a
1
) and the n-type MOSFET QN
1
possesses a drive characteristic curve (b
1
) as shown in FIG.
7
. These curves (a
1
) and (b
1
) intersect at a point V
1
=A
1
. On the other hand, the p-type MOSFET QP
2
of the second static inverter has a gate voltage V
1
equal to that of the p-type MOSFET QP
1
of the first inverter and has, therefore, a load characteristic curve (c
1
). With VREF=VBIT, the drive characteristic curve of the n-type MOSFET QN
2
of the second static inverter becomes equal to b
1
. Both the characteristic curves intersect at apoint of VOUT=A
1
. The drive characteristic of the n-type MOSFET QN
2
of the second static inverter, since the curves b
1
and c
1
intersect in a saturated region, changes to the curves d
1
and el with a small change in the bit-line potential. Therefore, the intersection of the curve b
1
with the load characteristic curve c
1
considerably shifts from the VOUT=B
1
to a point of VOUT=C
1
. Thus, a small voltage signal can be sensed and amplified faster at high sensitivity as the characteristic I of FIG.
7
.
Referring to
FIG. 1
, the operation of the amplifier circuit used in a multivalued information storing memory will be described below.
In an initial state of the sense-amplifier circuit, bit-lines (VBIT) and reference-lines (VREF) are usually pre-charged to set at an initial potential V0 (
FIG. 2
) before reading-out operation. A memory cell is then discharged, whereby the bit-line potential (VBIT) becomes to be one of the bit-line potentials (VTH
1
, VTH
2
, VTH
3
, VTH
4
) depending on the threshold of the memory cell. On the other hand, the reference line potential takes an intermediate potential value (VREF
1
, VREF
2
, VREF
3
) of the respective bit-lines. For example, when a bit-line potential VBIT is equal to VTH
2
according to the threshold of the memory cell to be readout, VBIT at the sub sense-amplifier SL
1
becomes higher than VREF
1
, VBIT at the sub sense-amplifier SL
2
becomes lower than VREF
2
and VBIT at the sub sense-amplifier SL
3
becomes lower than VREF
3
. At this time, the sub sense-amplifiers SL
1
, SL
2
and SL
3
have output signals SA
1
=
0
, SA
2
=
1
and SA
3
=
1
respectively and an output information (D
1
, D
2
)=(
0
,
1
) is obtained through a circuit shown in FIG.
3
. Similarly, an output information as shown in
FIG. 4
can be obtained when bit-line potentials are of VTH
1
, VTH
3
and VTH
4
.
In the current-mirror-type sense-amplifier, the transition of its output SA becomes slower with a smaller difference between a bit-line potential and a reference potential. Accordingly, each sub sense-amplifier having a small difference (&Dgr;V=|VBIT−VREF|) between a bit-line potential and a reference potential may have a considerable delay time of transition, by which the delay time of the sense amplifier circuit is defined. Consequently, the sense amplifier circuit of
FIG. 1
causes the memory to have an access time that is defined by SL
1
with a least difference value (&Dgr;V) at the bit-line potential being equal to VTH
1
, by SL
1
or SL
2
at VTH
2
, by SL
2
or SL
3
and by SL
3
at VTH
4
.
The sense-amplifier circuit used for a multivalued information storing memory is composed of a plurality of sub sense-amplifiers corresponding to respective reference potentials. If the sub sense-amplifiers are the same in construction, they have different sensitivity (gain) depending on the input potential signals irrespective of the same difference (&Dgr;V). The gain characteristics of the sub sense-amplifiers are shown in
FIGS. 7
,
8
and
9
.
In other words, the sense amplifier circuit may have an operating charact
Morrison & Foerster / LLP
Nguyen Hai L.
Sharp Kabushiki Kaisha
Wells Kenneth B.
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