Sense amplifier

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307279, 307DIG3, 365190, 365202, 365205, G11C 700

Patent

active

042740134

ABSTRACT:
An improved field effect transistor sense amplifier uses a cross-coupled pair of first transistors (Q1, Q2) with separate third and fourth transistors (Q3, Q4) connected by the sources (12, 14) to each of one of cross-coupled terminals (12, 14) of the cross-coupled pair (Q1, Q2). Read circuitry (Q7, Q8) is connected directly to the cross-coupled terminals (12, 14) of the cross-coupled pair (Q1, Q2). Write circuitry (Q9, Q10) is connected to the drains (18, 22) of the third and fourth transistors (Q3, Q4).

REFERENCES:
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Arzubi, "WRITE/SENSE Scheme for Monolithic Memories", IBM Tech. Discl. Bull., vol. 18, No. 8, pp. 2450-2451, Jan. 1976.
Heller et al., "High Sensitivity Charge-Transfer Sense Amplifier", IEEE-JSSC, vol. SC-11, No. 5, pp. 596-601, Oct. 1976.
Hoffmann et al., "VMOS Technology Applied to Dynamic RAM's", IEEE-JSSC, vol. SC-13, No. 5, pp. 618-622, Oct. 1978.
Meusburger et al., "An 8 mm.sup.2, 5V 16K Dynamic RAM Using a New Memory Cell", IEEE-JSSC, vol. SC-13, No. 5, pp. 708-711, Oct. 1978.

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