Sense-amp based adder with source follower evaluation tree

Details Sense-amp based adder with source follower evaluation tree Sense-amp based adder with source follower evaluation tree

2002-06-10

2004-09-07

Chang, Daniel D. (Department: 2819)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C326S095000

Reexamination Certificate

active

06789099

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is that of high speed CMOS logic, in particular that of lookahead adders.
BACKGROUND OF THE INVENTION
In the field of high speed dynamic CMOS circuits, there have been several efforts to reduce the delay of high fan-in circuits by using the dynamic differential circuit and sense-amplifier (sense-amp) together. Recent circuit styles use differential cascode voltage logic (DCVS) for the logic evaluation tree.
FIG. 1A
shows in simplified form, a prior art circuit diagram, including sense amp
1
and logic evaluation circuit
15
′. The CLK signals are applied to equilibrate the Q and Q# nodes (using the convention that Q# means the logic complement of Q) of the sense amp to VDD and the delayed CLK signal opens a current path to ground. Clocked footer transistors
16
and
16
′ provide the optional ability to cut off current flow te ground and cause the transistors in units
15
and
15
′ to float up to some voltage above ground.
Logic tree circuit
15
′ performs the logic analysis and applies a differential input to nodes Q and Q#. Sense amp
1
will respond to the differential signal once the difference exceeds the noise level and will drive nodes Q and Q# to the rails.
SUMMARY OF THE INVENTION
The invention relates to a multi-bit high speed adder employing a two level lookahead carry structure.
A feature of the invention is a 64-bit adder implemented in partially depleted silicon on insulator technology and having only two levels of lookahead carry implemented in sense-amp based differential logic.
Another feature of the invention is the use of a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier.
Yet another feature of the invention is the use of partially depleted silicon on insulator technology in the evaluation tree, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.


REFERENCES:
Kim et al., “SOI-optimized 64-bit high-speed CMOS adder design”, VLSI Circuits Digest of Technical Papers, 2002. Symposium on, Jun. 13-15, 2002, pp. 122-125.*
Matsui et al., “A 200 MHz 13 mm22-D DCT Macrocell Using Sense-Amplifying Pipeline Flip-Flop Scheme”, IEEE Journal of Solid-State Circuits, vol. 29. No. 12, Dec. 1994, pp. 1482-1490.
Lai et al. “Design and Implementation of Differential Cascode Voltage Swtich with Pass-Gate (DCVSPG) Logic for High-Performance Digital Systems”, IEEE Journal of Solid-State Circuits, vol. 32. No. 4, Apr. 1997, pp. 563-573.
Grotjohn et al., “Sample-Set Differential Logic (SSDL) for Complex High-Speed VLSI”, IEEE Journal of Solid-State Circuits, vol Sc-21. No. 2, Apr. 1986, pp. 367-368.
Pong-Fei Lu et al., “Floating-Body Effects in Partially Depleted SOI CMOS Circuits”, IEEE Journal of Solid-State Circuits, vol. 32. No. 8, Aug. 1997, pp. 1241-1253.
Park et al., “470ps 64bit Parallel Binary Adder”, VLSI Circuits Digest of Technical Papers, 2000, pp. 192-193.
Lu, “Implementation of Iterative Networks with CMOS Differential Logic”, IEEE Journal of Solid-State Circuits, vol. 23. No. 4, Aug. 1988, pp. 1013-1017.
Naffziger, “SP22.5: A Sub-Nanosecond 0.5 &mgr;m 64b Adder Design”, ISSCC96/Session 22/ Microprocessing Functional Blocks & Circuits/Paper SP22.5, Feb. 10, 1996, 2 pages.

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