Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
2007-10-09
2007-10-09
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C712S034000, C719S313000
Reexamination Certificate
active
11198042
ABSTRACT:
A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.
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Bridges Jeffrey Todd
Davis Gordon Taylor
Sartorius Thomas Andrew
Siegel Michael Steven
Cockburn Joscelyn G.
Connolly Bove & Lodge & Hutz LLP
Kim Kenneth S.
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