Coded data generation or conversion – Digital code to digital code converters – Parallel to serial
Reexamination Certificate
2006-06-20
2006-06-20
Nguyen, John B (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Parallel to serial
C341S100000
Reexamination Certificate
active
07064690
ABSTRACT:
A serializer and a deserializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the data when sending and de-serializes the data when receiving. A bit clock or pulse travels with the data word bits to define when a bit is stable. The system uses word boundary bits operating with a bit clock to distinguish different data words, as described in the parent application. The system operates either synchronously or asynchronously with the base computer or other such digital system, including I/O devices. The invention finds use where new data to be sent is strobed into the serializer, but also where a change in the data bit content itself will cause the changed data to be loaded into the serializer and sent bit by bit. The system operates where new data is strobed or loaded by the serializer (not the base computer system) when the last data word has been sent. In this case a signal is generated when the last word has been sent in the serializer that causes new data to be loaded for sending. Half duplex and full duplex configurations as disclosed. Similar, corresponding operations occur at the deserializer.
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Boomer James B.
Fowler Michael L.
Cesari and McKenna LLP
Fairchild Semiconductor Corporation
Nguyen John B
Paul, Esq. Edwin H.
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