Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
2000-08-21
2004-02-24
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S211000, C257S691000
Reexamination Certificate
active
06696712
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semicustom IC such as a gate array and a standard cell.
BACKGROUND ART
FIGS. 6 and 7
illustrate one conventional semicustom IC, wherein
FIG. 6
is a plan view and
FIG. 7
is a cross-sectional view thereof taken along line B—B.
As shown in
FIGS. 6 and 7
, the semicustom IC includes a plurality of basic cells
3
a
,
3
b
, . . . ,
3
n
which are densely disposed side by side on a semiconductor substrate
1
, wherein a first macrocell
2
a
is formed using basic cells
3
c
and
3
d
and also using interconnection lines in two interconnection layers, a first interconnection layer
7
and a second interconnection layer
9
, extending over the basic cells
3
c
and
3
d.
Furthermore, in this semicustom IC, as shown in
FIGS. 6 and 7
, ring-shaped power supply lines
4
and
5
for supplying a specific voltage to the first macrocell
2
a
are formed using interconnection lines in the first interconnection layer
7
and the second interconnection layer
9
extending around the first macrocell
2
a.
In this semicustom IC, as shown in
FIGS. 6 and 7
, a second macrocell
2
b
is formed using the basic cell
3
a
located outside the power supply lines
4
and
5
and also using interconnection lines in the first interconnection layer
7
and the second interconnection layer
9
, extending over the basic cell
3
a.
The semicustom IC is described in further detail below. As shown in
FIG. 7
, an insulating layer
6
is formed on the semiconductor substrate
1
on which the plurality of basic cells
3
a
,
3
b
, . . . ,
3
n
are formed. On the insulating layer
6
, an interconnection conductor
71
used as a signal interconnection line for the first macrocell
2
a
is formed in the first interconnection layer
7
, and an interconnection conductor
72
used as a signal interconnection line for the second macrocell
2
b
is formed in the first interconnection layer
7
.
In the first macrocell
2
a
, the basic cells
3
c
and
3
d
are electrically connected to the interconnection conductor
71
via connecting conductors (through-hole)
74
extending in the thickness direction through the insulating layer
6
. In the second macrocell
2
b
, the basic cell
3
a
is electrically connected to the interconnection conductor
72
via connecting conductors
75
extending in the thickness direction through the insulating layer
6
.
An insulating layer
8
is formed on the first interconnection layer
7
as shown in FIG.
7
. On the insulating layer
8
, an interconnection conductor
91
used as a signal interconnection line for the first macrocell
2
a
is formed in the second interconnection layer
9
, and an interconnection conductor
92
used as a signal interconnection line for the second macrocell
2
b
is formed in the second interconnection layer
9
. The interconnection conductor
71
and the interconnection conductor
91
are electrically connected to each other via connecting conductors
94
extending in the thickness direction through the insulating layer
8
. Similarly, the interconnection conductor
72
and the interconnection conductor
92
are electrically connected to each other via connecting conductors
95
extending in the thickness direction through the insulating layer
8
.
In the conventional semicustom IC constructed in the above-described manner, the first macrocell
2
a
is formed so as to have a desired function using basic cells
3
c
and
3
d
formed on the semiconductor substrate
1
and also using the interconnection conductor
71
in the first interconnection layer
7
and the interconnection conductor
91
in the second interconnection layer
9
. Similarly, the second macrocell
2
b
is formed so as to have a desired function using the basic cell
3
a
formed on the semiconductor substrate
1
and also using the interconnection conductor
72
in the first interconnection layer
7
and the interconnection conductor
92
in the second interconnection layer
9
.
The detailed structures of the power supply lines
4
and
5
are described below with reference to
FIGS. 6 and 7
.
The power supply line
4
includes an interconnection conductor
41
, in the first interconnection layer
7
, extending horizontally (in
FIG. 6
) on the insulating layer
6
and also includes an interconnection conductor
42
, in the second interconnection layer
9
, extending vertically (in
FIG. 6
) on the insulating layer
8
, wherein the interconnection conductor
41
and the interconnection conductor
42
are connected to each other via a connecting conductor
43
extending in the thickness direction through the insulating layer
8
such that a closed circuit is formed. Similarly, the power supply line
5
includes an interconnection conductor
51
, in the first interconnection layer
7
, extending horizontally on the insulating layer
6
and also includes an interconnection conductor
52
, in the second interconnection layer
9
, extending vertically on the insulating layer
8
, wherein the interconnection conductor
51
and the interconnection conductor
52
are connected to each other via a connecting conductor
53
extending in the thickness direction through the insulating layer
8
such that a closed circuit is formed.
The first macrocell
2
a
forms, for example, a memory, and the second macrocell
2
b
located outside the power supply lines
4
and
5
forms, for example, a battery backup circuit for holding data stored in the memory.
In the case where the memory is formed in the first macrocell
2
a
of the conventional semicustom IC described above, the battery backup circuit is formed in the second macrocell
2
b
using the basic cell
3
a
located outside the power supply lines
4
and
5
.
However, in this case, because the second macrocell
2
b
is formed outside the power supply lines
4
and
5
, the space needed to form the second macrocell
2
b
results in an increase in the total size.
The above problem may be avoided if the basic cell
3
b
, which is located closest to the first macro cell
2
a
as shown in
FIG. 7
, can be used. However, the power supply lines
4
and
5
extending directly above the basic cell
3
b
make it impossible to use the basic cell
3
b
for such a purpose.
Aspects of the present invention to provide a semicustom IC which includes a large number of basic cells formed on a semiconductor substrate and which allows a plurality of macro cells to be formed using basic cells in an efficient manner thereby allowing a reduction in the total size of the semicustom IC. The present invention provides a semicustom IC including a plurality of basic cells disposed on a semiconductor substrate, a first macrocell, a second macrocell adjacent to the first macrocell, and a power supply line The first macrocell and second macrocell are each formed using at least one basic cell and a plurality of interconnection layers. The first macrocell is formed using first basic cells of the plurality of basic cells and using interconnection layers disposed over the first basic cells. The power supply line is for supplying power to the first macrocell, and is formed around the first macrocell using an upper interconnection layer of the plurality of interconnection layers. The second macrocell is formed below the power supply line using a basic cell and a lower interconnection layer, extending over the basic cell, of the plurality of interconnection layers.
In other embodiments, the interconnection layers can include three or more interconnection layers.
Because the second macrocell can be formed using the basic cell at the location closest to the first macrocell, the basic cells can be used in an efficient manner, and the total size can be reduced.
In other embodiments, the plurality of interconnection layers can include a total of four interconnection layers and the power supply line is formed using a third interconnection layer and a fourth interconnection layer of the total of four interconnection layers.
In other embodiments, the third and fourth interconnection layers of the total of four interconnection layers ca
Hogan & Hartson LLP
Seiko Epson Corporation
Thomas Tom
Vu Hung Kim
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