Semicustom chip whose logic cells have narrow tops and wide bott

Details Semicustom chip whose logic cells have narrow tops and wide bott Semicustom chip whose logic cells have narrow tops and wide bott

1987-03-31

1990-08-14

James, Andrew J.

357 35, 357 40, 357 41, H01L 2710, H01L 2702, H01L 2972

Patent

active

049491490

ABSTRACT:
A logic cell, for use in a semicustom chip, is comprised of a plurality of transistors that are integrated into a semiconductor substrate and are interconnected within the cell to perform a logic function. This cell has sidewalls which define the space in the chip which contains all the transistors and their interconnections within the cell; at least one of the sidewalls is shaped to include a step which gives the cell a narrow top and a wide bottom; and one or more of the cell's transistors lies below the step in the wide bottom of the cell. Many of these cells are arranged in spaced apart rows on the semicustom chip in which the narrow tops of the cell line up. Conductors which interconnect the cells are disposed in the space between the narrow tops of the cells and over the transistors in the wide bottoms of the cells. Using this architecture, the density with which a logic cell is integrated to a semicustom chip is improved more than 100%.

REFERENCES:
patent: 4006492 (1977-02-01), Eichelberger et al.
patent: 4381201 (1983-04-01), Sakurai
patent: 4500905 (1985-02-01), Shibata
patent: 4589007 (1986-05-01), Kuboki et al.
patent: 4644382 (1987-02-01), Charransol et al.
patent: 4646266 (1987-02-01), Ovshinsky et al.

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