Semiconductor wafer with rear side identification and method

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Mesa structure

Reexamination Certificate

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Details

C257S624000, C257S628000, C257SE23178, C438S014000, C438S033000

Reexamination Certificate

active

07911036

ABSTRACT:
A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.

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patent: 10 2004 048 202 (2006-04-01), None
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patent: WO98/52226 (1998-11-01), None
patent: WO03/065576 (2003-08-01), None
patent: WO2006/034683 (2006-04-01), None
“Lithographic Chip Identification: Meeting the Failure Analysis Challenge”, Lynn Dwyer, Kevin Riddell, SPIE, vol. 1673 Integrated Circuit Metrology, Inspection and Process Control VI, (1992)/615.

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