Semiconductor wafer with enhanced pre-process denudation and pro

Details Semiconductor wafer with enhanced pre-process denudation and pro Semiconductor wafer with enhanced pre-process denudation and pro

1994-03-07

1995-08-29

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 13, 148DIG60, H01L 21324

Patent

active

054459753

ABSTRACT:
A method is provided for pre-process denudation and process-induced gettering of a CZ silicon wafer having one or more monolithic devices embodied therein. Pre-process denudation is performed in a hydrogen ambient to out-diffuse oxygen as well as to maintain interstitial silicon flux away from the substrate surface. Process-induced gettering is performed at a low temperature to ensure stacking faults and surface irregularities do not arise from interstitial silicon bonding at the surface prior to gate oxidation. The third step of the denudation/gettering cycle involving precipitate growth is thereby delayed or forestalled until the field oxide is grown. Any changes or movement in oxygen and/or interstitial silicon within or near the substrate surface occurring after polysilicon deposition will have minimal effect upon the established gate oxide. Accordingly, gate oxide integrity (e.g., breakdown voltage and uniformity) are enhanced by the present process.

REFERENCES:
patent: 4548654 (1985-10-01), Tobin
patent: 4666532 (1987-05-01), Korb et al.
patent: 5162241 (1992-11-01), Mori et al.
Wolf, "Silicon Processing for the VLSI Era" vol. 2, Process Integration, pp. 314-315, Copyright .COPYRGT.1990 by Lattice Press.
Borland, "Borland's Overview of the Latest in Intrinsic Gettering: Part I", Semiconductor International, (Apr. 1989), pp. 144-148.
Borland, "Borland's Overview of the Latest in Intrinsic Gettering: Part II", Semiconductor International, (Apr. 1989), pp. 154-157.
Borland, et al. "MeV Implantation Technology: Next-Generation Manufacturing with Current-Generation Equipment", Solid State Technology, (Dec. 1993), pp. 1-8.
Borland, et al., "Advanced CMOS Epitaxial Processing for Latch-Up Hardening and Improved Epilayer Quality", Solid State Technology, (Aug. 1984), pp. 123-131.

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