Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2002-09-13
2004-05-11
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S738000, C257S778000, C257S779000, C257S780000, C257S786000, C228S180220
Reexamination Certificate
active
06734554
ABSTRACT:
Japanese Patent Application Nos. 2001-283978 filed on Sep. 18, 2001, and 2002-223483 filed on Jul. 31, 2002 are hereby incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor wafer, a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.
A bump electrode is useful as an external connecting terminal to reduce a semiconductor package and a semiconductor package disposing area on the substrate. A tape carrier-package utilizing the TAB (Tape Automated Bonding) system and a flip chip structure such as the CSP (Chip Size/Scale Package), etc. are practically used by using the bump electrode.
FIG. 15
is a schematic view of an external connecting portion in a conventional semiconductor chip. A bump is arranged in a pad. The bump is typically constructed by a solder bump and an Au bump. There is an electrolytic plating method as a forming method of this bump.
A patterned wiring layer and pads
510
are formed in a semiconductor wafer
500
forming the bump, and its periphery is coated with a protection film (passivation film)
520
except for an electric connecting area surface of the pad
510
. A barrier metal layer and a close attaching metal layer (an under bump metal
530
) are laminated on the pad
510
by the sputtering method. Thereafter, an unillustrated resist for bump formation exposing the electric connecting area of the pad and its peripheral portion is formed by the photolithography technique.
Next, a predetermined metal is plated and grown by the electrolytic plating method in accordance with the pattern of the resist. In other words, the semiconductor wafer
500
is dipped into an electrolytic plating liquid, and an electric current flows to the semiconductor wafer
500
through the under bump metal
530
. Thus, a predetermined metal for the bump is deposited and grown. Thereafter, the resist is separated and the under bump metal
530
is then wet-etched in accordance with the kind of each layer with the plated and grown metal as a mask. Thereafter, a bump
540
is formed via anneal, etc.
In the electrolytic plating method, it is necessary that no plating height is dispersed on the surface of the semiconductor wafer
500
. In other words, the plating height in a chip area near an outer circumferential portion of the semiconductor wafer
500
tends to be high in comparison with that near the center of the semiconductor wafer
500
. A portion near the outer circumferential portion of the semiconductor wafer
500
is located at an electric current terminal, and a high electric field might be caused in this portion. When ununiformity of the height of the bump
540
becomes not able, a chip treated as a defective product even in the area of an effective chip is generated. Therefore, the bump
540
of a height exceeding a tolerance in the chip near the outer circumference of the semiconductor wafer
500
was constructed and a measure had to be taken so as not to reduce the effective chip.
BRIEF SUMMARY OF THE INVENTION
A semiconductor wafer in one aspect of the present invention includes a plurality of semiconductor chips, the semiconductor wafer comprising:
first semiconductor chips including a side of the semiconductor wafer;
second semiconductor chips formed in an area surrounded by the first semiconductor chips, each of the second semiconductor chips having at least an integrated circuit and pads electrically connected to the integrated circuit;
first bumps formed over each of the first semiconductor chips, at least part of each of the first bumps being formed in a columnar shape; and
second bumps formed over the pads, respectively, at least part of each of the second bumps being formed in a columnar shape.
A semiconductor wafer in another aspect of the present invention includes a plurality of semiconductor chips, the semiconductor wafer comprising:
first semiconductor chips including a side of the semiconductor wafer;
second semiconductor chips formed in an area surrounded by the first semiconductor chips, each of the second semiconductor chips having at least an integrated circuit and pads electrically connected to the integrated circuit;
first bumps formed over each of the first semiconductor chips by a plating method; and
second bumps formed over the pads, respectively, by the plating method.
A semiconductor wafer in a further aspect of the present invention includes a plurality of semiconductor chips, the semiconductor wafer comprising:
first semiconductor chips, each of which is surrounded by cutting lines for cutting the semiconductor wafer into individual pieces of the semiconductor chips and by at least part of a side of the semiconductor wafer;
second semiconductor chips, each of which is surrounded by the cutting lines only and has an integrated circuit and pads electrically connected to the integrated circuit;
first bumps formed over each of the first semiconductor chips, at least part of each of the first bumps being formed in a columnar shape; and
second bumps formed over the pads, respectively, at least part of each of the second bumps being formed in a columnar shape.
A method of manufacturing a semiconductor device in a still further aspect of the present invention includes:
forming first bumps over each of first semiconductor chips including a side of a semiconductor wafer by a plating method;
forming second bumps over each of second semiconductor chips formed in an area surrounded by the first semiconductor chips, each of the second semiconductor chips having at least an integrated circuit and pads electrically connected to the integrated circuit by a plating method; and
cutting the semiconductor wafer into individual pieces of the first semiconductor chips and the second semiconductor chips.
A method of manufacturing a semiconductor device in a still further aspect of the present invention includes:
forming a first mask having first openings over first semiconductor chips including a side of a semiconductor wafer;
forming first bumps over each of the first semiconductor chips by forming a conductive layer at least in each of the first openings;
forming a second mask having second openings over second semiconductor chips formed in an area surrounded by the first semiconductor chips, each of the second semiconductor chips having at least an integrated circuit and pads electrically connected to the integrated circuit;
forming second bumps over each of the second semiconductor chips by forming a conductive layer at least in each of the second openings; and
cutting the semiconductor wafer into individual pieces of the first semiconductor chips and the second semiconductor chips.
A method of manufacturing a semiconductor device in a still further the present invention includes:
forming first bumps over each of first semiconductor chips surrounded by cutting lines for cutting a semiconductor wafer into individual pieces of semiconductor chips in a subsequent cutting step and by at least part of a side of the semiconductor wafer;
forming second bumps over each of second semiconductor chips surrounded by the cutting lines only and having an integrated circuit and pads electrically connected to the integrated circuit; and
cutting the semiconductor wafer into individual pieces of the first semiconductor chips and the second semiconductor chips.
A semiconductor device in an even further aspect of the present invention is manufactured by the above method.
A circuit board in a yet further aspect the present invention has the above semiconductor device mounted thereon.
An electronic device in an even more further aspect of the present invention has the above semiconductor device.
REFERENCES:
patent: 6074896 (2000-06-01), Dando
patent: 6303470 (2001-10-01), Ohsumi et al.
patent: 6544821 (2003-04-01), Akram
patent: 2000068271 (2000-03-01), None
patent: 2000106382 (2000-04-01), None
patent: 2001085457 (2001-03-01), None
patent: 2001223288 (2001-08-01), None
Chambliss Alonzo
Oliff & Berridg,e PLC
Seiko Epson Corporation
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